\ STM32F0xx Register Bitfield Definitions for Mecrisp-Stellaris Forth by Matthias Koch. \ bitfield.xsl takes STM32Fxx.svd, config.xml and produces bitfield.fs \ Written by Terry Porter "terry@tjporter.com.au" 2016 - 2018 and released under the GPL V2. \ Replace 'bi?' with 'bit@' to test bit, 'bis!' to SET bit, 'bic!' to CLEAR bit etc. \ GPIOC_MODER (read-write) : GPIOC_MODER_MODER15 ( %XX -- ) 30 lshift GPIOC_MODER bis! ; \ GPIOC_MODER_MODER15 Port x configuration bits y = 0..15 : GPIOC_MODER_MODER14 ( %XX -- ) 28 lshift GPIOC_MODER bis! ; \ GPIOC_MODER_MODER14 Port x configuration bits y = 0..15 : GPIOC_MODER_MODER13 ( %XX -- ) 26 lshift GPIOC_MODER bis! ; \ GPIOC_MODER_MODER13 Port x configuration bits y = 0..15 : GPIOC_MODER_MODER12 ( %XX -- ) 24 lshift GPIOC_MODER bis! ; \ GPIOC_MODER_MODER12 Port x configuration bits y = 0..15 : GPIOC_MODER_MODER11 ( %XX -- ) 22 lshift GPIOC_MODER bis! ; \ GPIOC_MODER_MODER11 Port x configuration bits y = 0..15 : GPIOC_MODER_MODER10 ( %XX -- ) 20 lshift GPIOC_MODER bis! ; \ GPIOC_MODER_MODER10 Port x configuration bits y = 0..15 : GPIOC_MODER_MODER9 ( %XX -- ) 18 lshift GPIOC_MODER bis! ; \ GPIOC_MODER_MODER9 Port x configuration bits y = 0..15 : GPIOC_MODER_MODER8 ( %XX -- ) 16 lshift GPIOC_MODER bis! ; \ GPIOC_MODER_MODER8 Port x configuration bits y = 0..15 : GPIOC_MODER_MODER7 ( %XX -- ) 14 lshift GPIOC_MODER bis! ; \ GPIOC_MODER_MODER7 Port x configuration bits y = 0..15 : GPIOC_MODER_MODER6 ( %XX -- ) 12 lshift GPIOC_MODER bis! ; \ GPIOC_MODER_MODER6 Port x configuration bits y = 0..15 : GPIOC_MODER_MODER5 ( %XX -- ) 10 lshift GPIOC_MODER bis! ; \ GPIOC_MODER_MODER5 Port x configuration bits y = 0..15 : GPIOC_MODER_MODER4 ( %XX -- ) 8 lshift GPIOC_MODER bis! ; \ GPIOC_MODER_MODER4 Port x configuration bits y = 0..15 : GPIOC_MODER_MODER3 ( %XX -- ) 6 lshift GPIOC_MODER bis! ; \ GPIOC_MODER_MODER3 Port x configuration bits y = 0..15 : GPIOC_MODER_MODER2 ( %XX -- ) 4 lshift GPIOC_MODER bis! ; \ GPIOC_MODER_MODER2 Port x configuration bits y = 0..15 : GPIOC_MODER_MODER1 ( %XX -- ) 2 lshift GPIOC_MODER bis! ; \ GPIOC_MODER_MODER1 Port x configuration bits y = 0..15 : GPIOC_MODER_MODER0 ( %XX -- ) 0 lshift GPIOC_MODER bis! ; \ GPIOC_MODER_MODER0 Port x configuration bits y = 0..15 \ GPIOC_OTYPER (read-write) : GPIOC_OTYPER_OT15 %1 15 lshift GPIOC_OTYPER bis! ; \ GPIOC_OTYPER_OT15 Port x configuration bit 15 : GPIOC_OTYPER_OT14 %1 14 lshift GPIOC_OTYPER bis! ; \ GPIOC_OTYPER_OT14 Port x configuration bit 14 : GPIOC_OTYPER_OT13 %1 13 lshift GPIOC_OTYPER bis! ; \ GPIOC_OTYPER_OT13 Port x configuration bit 13 : GPIOC_OTYPER_OT12 %1 12 lshift GPIOC_OTYPER bis! ; \ GPIOC_OTYPER_OT12 Port x configuration bit 12 : GPIOC_OTYPER_OT11 %1 11 lshift GPIOC_OTYPER bis! ; \ GPIOC_OTYPER_OT11 Port x configuration bit 11 : GPIOC_OTYPER_OT10 %1 10 lshift GPIOC_OTYPER bis! ; \ GPIOC_OTYPER_OT10 Port x configuration bit 10 : GPIOC_OTYPER_OT9 %1 9 lshift GPIOC_OTYPER bis! ; \ GPIOC_OTYPER_OT9 Port x configuration bit 9 : GPIOC_OTYPER_OT8 %1 8 lshift GPIOC_OTYPER bis! ; \ GPIOC_OTYPER_OT8 Port x configuration bit 8 : GPIOC_OTYPER_OT7 %1 7 lshift GPIOC_OTYPER bis! ; \ GPIOC_OTYPER_OT7 Port x configuration bit 7 : GPIOC_OTYPER_OT6 %1 6 lshift GPIOC_OTYPER bis! ; \ GPIOC_OTYPER_OT6 Port x configuration bit 6 : GPIOC_OTYPER_OT5 %1 5 lshift GPIOC_OTYPER bis! ; \ GPIOC_OTYPER_OT5 Port x configuration bit 5 : GPIOC_OTYPER_OT4 %1 4 lshift GPIOC_OTYPER bis! ; \ GPIOC_OTYPER_OT4 Port x configuration bit 4 : GPIOC_OTYPER_OT3 %1 3 lshift GPIOC_OTYPER bis! ; \ GPIOC_OTYPER_OT3 Port x configuration bit 3 : GPIOC_OTYPER_OT2 %1 2 lshift GPIOC_OTYPER bis! ; \ GPIOC_OTYPER_OT2 Port x configuration bit 2 : GPIOC_OTYPER_OT1 %1 1 lshift GPIOC_OTYPER bis! ; \ GPIOC_OTYPER_OT1 Port x configuration bit 1 : GPIOC_OTYPER_OT0 %1 0 lshift GPIOC_OTYPER bis! ; \ GPIOC_OTYPER_OT0 Port x configuration bit 0 \ GPIOC_OSPEEDR (read-write) : GPIOC_OSPEEDR_OSPEEDR15 ( %XX -- ) 30 lshift GPIOC_OSPEEDR bis! ; \ GPIOC_OSPEEDR_OSPEEDR15 Port x configuration bits y = 0..15 : GPIOC_OSPEEDR_OSPEEDR14 ( %XX -- ) 28 lshift GPIOC_OSPEEDR bis! ; \ GPIOC_OSPEEDR_OSPEEDR14 Port x configuration bits y = 0..15 : GPIOC_OSPEEDR_OSPEEDR13 ( %XX -- ) 26 lshift GPIOC_OSPEEDR bis! ; \ GPIOC_OSPEEDR_OSPEEDR13 Port x configuration bits y = 0..15 : GPIOC_OSPEEDR_OSPEEDR12 ( %XX -- ) 24 lshift GPIOC_OSPEEDR bis! ; \ GPIOC_OSPEEDR_OSPEEDR12 Port x configuration bits y = 0..15 : GPIOC_OSPEEDR_OSPEEDR11 ( %XX -- ) 22 lshift GPIOC_OSPEEDR bis! ; \ GPIOC_OSPEEDR_OSPEEDR11 Port x configuration bits y = 0..15 : GPIOC_OSPEEDR_OSPEEDR10 ( %XX -- ) 20 lshift GPIOC_OSPEEDR bis! ; \ GPIOC_OSPEEDR_OSPEEDR10 Port x configuration bits y = 0..15 : GPIOC_OSPEEDR_OSPEEDR9 ( %XX -- ) 18 lshift GPIOC_OSPEEDR bis! ; \ GPIOC_OSPEEDR_OSPEEDR9 Port x configuration bits y = 0..15 : GPIOC_OSPEEDR_OSPEEDR8 ( %XX -- ) 16 lshift GPIOC_OSPEEDR bis! ; \ GPIOC_OSPEEDR_OSPEEDR8 Port x configuration bits y = 0..15 : GPIOC_OSPEEDR_OSPEEDR7 ( %XX -- ) 14 lshift GPIOC_OSPEEDR bis! ; \ GPIOC_OSPEEDR_OSPEEDR7 Port x configuration bits y = 0..15 : GPIOC_OSPEEDR_OSPEEDR6 ( %XX -- ) 12 lshift GPIOC_OSPEEDR bis! ; \ GPIOC_OSPEEDR_OSPEEDR6 Port x configuration bits y = 0..15 : GPIOC_OSPEEDR_OSPEEDR5 ( %XX -- ) 10 lshift GPIOC_OSPEEDR bis! ; \ GPIOC_OSPEEDR_OSPEEDR5 Port x configuration bits y = 0..15 : GPIOC_OSPEEDR_OSPEEDR4 ( %XX -- ) 8 lshift GPIOC_OSPEEDR bis! ; \ GPIOC_OSPEEDR_OSPEEDR4 Port x configuration bits y = 0..15 : GPIOC_OSPEEDR_OSPEEDR3 ( %XX -- ) 6 lshift GPIOC_OSPEEDR bis! ; \ GPIOC_OSPEEDR_OSPEEDR3 Port x configuration bits y = 0..15 : GPIOC_OSPEEDR_OSPEEDR2 ( %XX -- ) 4 lshift GPIOC_OSPEEDR bis! ; \ GPIOC_OSPEEDR_OSPEEDR2 Port x configuration bits y = 0..15 : GPIOC_OSPEEDR_OSPEEDR1 ( %XX -- ) 2 lshift GPIOC_OSPEEDR bis! ; \ GPIOC_OSPEEDR_OSPEEDR1 Port x configuration bits y = 0..15 : GPIOC_OSPEEDR_OSPEEDR0 ( %XX -- ) 0 lshift GPIOC_OSPEEDR bis! ; \ GPIOC_OSPEEDR_OSPEEDR0 Port x configuration bits y = 0..15 \ GPIOC_PUPDR (read-write) : GPIOC_PUPDR_PUPDR15 ( %XX -- ) 30 lshift GPIOC_PUPDR bis! ; \ GPIOC_PUPDR_PUPDR15 Port x configuration bits y = 0..15 : GPIOC_PUPDR_PUPDR14 ( %XX -- ) 28 lshift GPIOC_PUPDR bis! ; \ GPIOC_PUPDR_PUPDR14 Port x configuration bits y = 0..15 : GPIOC_PUPDR_PUPDR13 ( %XX -- ) 26 lshift GPIOC_PUPDR bis! ; \ GPIOC_PUPDR_PUPDR13 Port x configuration bits y = 0..15 : GPIOC_PUPDR_PUPDR12 ( %XX -- ) 24 lshift GPIOC_PUPDR bis! ; \ GPIOC_PUPDR_PUPDR12 Port x configuration bits y = 0..15 : GPIOC_PUPDR_PUPDR11 ( %XX -- ) 22 lshift GPIOC_PUPDR bis! ; \ GPIOC_PUPDR_PUPDR11 Port x configuration bits y = 0..15 : GPIOC_PUPDR_PUPDR10 ( %XX -- ) 20 lshift GPIOC_PUPDR bis! ; \ GPIOC_PUPDR_PUPDR10 Port x configuration bits y = 0..15 : GPIOC_PUPDR_PUPDR9 ( %XX -- ) 18 lshift GPIOC_PUPDR bis! ; \ GPIOC_PUPDR_PUPDR9 Port x configuration bits y = 0..15 : GPIOC_PUPDR_PUPDR8 ( %XX -- ) 16 lshift GPIOC_PUPDR bis! ; \ GPIOC_PUPDR_PUPDR8 Port x configuration bits y = 0..15 : GPIOC_PUPDR_PUPDR7 ( %XX -- ) 14 lshift GPIOC_PUPDR bis! ; \ GPIOC_PUPDR_PUPDR7 Port x configuration bits y = 0..15 : GPIOC_PUPDR_PUPDR6 ( %XX -- ) 12 lshift GPIOC_PUPDR bis! ; \ GPIOC_PUPDR_PUPDR6 Port x configuration bits y = 0..15 : GPIOC_PUPDR_PUPDR5 ( %XX -- ) 10 lshift GPIOC_PUPDR bis! ; \ GPIOC_PUPDR_PUPDR5 Port x configuration bits y = 0..15 : GPIOC_PUPDR_PUPDR4 ( %XX -- ) 8 lshift GPIOC_PUPDR bis! ; \ GPIOC_PUPDR_PUPDR4 Port x configuration bits y = 0..15 : GPIOC_PUPDR_PUPDR3 ( %XX -- ) 6 lshift GPIOC_PUPDR bis! ; \ GPIOC_PUPDR_PUPDR3 Port x configuration bits y = 0..15 : GPIOC_PUPDR_PUPDR2 ( %XX -- ) 4 lshift GPIOC_PUPDR bis! ; \ GPIOC_PUPDR_PUPDR2 Port x configuration bits y = 0..15 : GPIOC_PUPDR_PUPDR1 ( %XX -- ) 2 lshift GPIOC_PUPDR bis! ; \ GPIOC_PUPDR_PUPDR1 Port x configuration bits y = 0..15 : GPIOC_PUPDR_PUPDR0 ( %XX -- ) 0 lshift GPIOC_PUPDR bis! ; \ GPIOC_PUPDR_PUPDR0 Port x configuration bits y = 0..15 \ GPIOC_IDR (read-only) : GPIOC_IDR_IDR15 %1 15 lshift GPIOC_IDR bis! ; \ GPIOC_IDR_IDR15 Port input data y = 0..15 : GPIOC_IDR_IDR14 %1 14 lshift GPIOC_IDR bis! ; \ GPIOC_IDR_IDR14 Port input data y = 0..15 : GPIOC_IDR_IDR13 %1 13 lshift GPIOC_IDR bis! ; \ GPIOC_IDR_IDR13 Port input data y = 0..15 : GPIOC_IDR_IDR12 %1 12 lshift GPIOC_IDR bis! ; \ GPIOC_IDR_IDR12 Port input data y = 0..15 : GPIOC_IDR_IDR11 %1 11 lshift GPIOC_IDR bis! ; \ GPIOC_IDR_IDR11 Port input data y = 0..15 : GPIOC_IDR_IDR10 %1 10 lshift GPIOC_IDR bis! ; \ GPIOC_IDR_IDR10 Port input data y = 0..15 : GPIOC_IDR_IDR9 %1 9 lshift GPIOC_IDR bis! ; \ GPIOC_IDR_IDR9 Port input data y = 0..15 : GPIOC_IDR_IDR8 %1 8 lshift GPIOC_IDR bis! ; \ GPIOC_IDR_IDR8 Port input data y = 0..15 : GPIOC_IDR_IDR7 %1 7 lshift GPIOC_IDR bis! ; \ GPIOC_IDR_IDR7 Port input data y = 0..15 : GPIOC_IDR_IDR6 %1 6 lshift GPIOC_IDR bis! ; \ GPIOC_IDR_IDR6 Port input data y = 0..15 : GPIOC_IDR_IDR5 %1 5 lshift GPIOC_IDR bis! ; \ GPIOC_IDR_IDR5 Port input data y = 0..15 : GPIOC_IDR_IDR4 %1 4 lshift GPIOC_IDR bis! ; \ GPIOC_IDR_IDR4 Port input data y = 0..15 : GPIOC_IDR_IDR3 %1 3 lshift GPIOC_IDR bis! ; \ GPIOC_IDR_IDR3 Port input data y = 0..15 : GPIOC_IDR_IDR2 %1 2 lshift GPIOC_IDR bis! ; \ GPIOC_IDR_IDR2 Port input data y = 0..15 : GPIOC_IDR_IDR1 %1 1 lshift GPIOC_IDR bis! ; \ GPIOC_IDR_IDR1 Port input data y = 0..15 : GPIOC_IDR_IDR0 %1 0 lshift GPIOC_IDR bis! ; \ GPIOC_IDR_IDR0 Port input data y = 0..15 \ GPIOC_ODR (read-write) : GPIOC_ODR_ODR15 %1 15 lshift GPIOC_ODR bis! ; \ GPIOC_ODR_ODR15 Port output data y = 0..15 : GPIOC_ODR_ODR14 %1 14 lshift GPIOC_ODR bis! ; \ GPIOC_ODR_ODR14 Port output data y = 0..15 : GPIOC_ODR_ODR13 %1 13 lshift GPIOC_ODR bis! ; \ GPIOC_ODR_ODR13 Port output data y = 0..15 : GPIOC_ODR_ODR12 %1 12 lshift GPIOC_ODR bis! ; \ GPIOC_ODR_ODR12 Port output data y = 0..15 : GPIOC_ODR_ODR11 %1 11 lshift GPIOC_ODR bis! ; \ GPIOC_ODR_ODR11 Port output data y = 0..15 : GPIOC_ODR_ODR10 %1 10 lshift GPIOC_ODR bis! ; \ GPIOC_ODR_ODR10 Port output data y = 0..15 : GPIOC_ODR_ODR9 %1 9 lshift GPIOC_ODR bis! ; \ GPIOC_ODR_ODR9 Port output data y = 0..15 : GPIOC_ODR_ODR8 %1 8 lshift GPIOC_ODR bis! ; \ GPIOC_ODR_ODR8 Port output data y = 0..15 : GPIOC_ODR_ODR7 %1 7 lshift GPIOC_ODR bis! ; \ GPIOC_ODR_ODR7 Port output data y = 0..15 : GPIOC_ODR_ODR6 %1 6 lshift GPIOC_ODR bis! ; \ GPIOC_ODR_ODR6 Port output data y = 0..15 : GPIOC_ODR_ODR5 %1 5 lshift GPIOC_ODR bis! ; \ GPIOC_ODR_ODR5 Port output data y = 0..15 : GPIOC_ODR_ODR4 %1 4 lshift GPIOC_ODR bis! ; \ GPIOC_ODR_ODR4 Port output data y = 0..15 : GPIOC_ODR_ODR3 %1 3 lshift GPIOC_ODR bis! ; \ GPIOC_ODR_ODR3 Port output data y = 0..15 : GPIOC_ODR_ODR2 %1 2 lshift GPIOC_ODR bis! ; \ GPIOC_ODR_ODR2 Port output data y = 0..15 : GPIOC_ODR_ODR1 %1 1 lshift GPIOC_ODR bis! ; \ GPIOC_ODR_ODR1 Port output data y = 0..15 : GPIOC_ODR_ODR0 %1 0 lshift GPIOC_ODR bis! ; \ GPIOC_ODR_ODR0 Port output data y = 0..15 \ GPIOC_BSRR (write-only) : GPIOC_BSRR_BR15 %1 31 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BR15 Port x reset bit y y = 0..15 : GPIOC_BSRR_BR14 %1 30 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BR14 Port x reset bit y y = 0..15 : GPIOC_BSRR_BR13 %1 29 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BR13 Port x reset bit y y = 0..15 : GPIOC_BSRR_BR12 %1 28 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BR12 Port x reset bit y y = 0..15 : GPIOC_BSRR_BR11 %1 27 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BR11 Port x reset bit y y = 0..15 : GPIOC_BSRR_BR10 %1 26 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BR10 Port x reset bit y y = 0..15 : GPIOC_BSRR_BR9 %1 25 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BR9 Port x reset bit y y = 0..15 : GPIOC_BSRR_BR8 %1 24 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BR8 Port x reset bit y y = 0..15 : GPIOC_BSRR_BR7 %1 23 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BR7 Port x reset bit y y = 0..15 : GPIOC_BSRR_BR6 %1 22 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BR6 Port x reset bit y y = 0..15 : GPIOC_BSRR_BR5 %1 21 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BR5 Port x reset bit y y = 0..15 : GPIOC_BSRR_BR4 %1 20 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BR4 Port x reset bit y y = 0..15 : GPIOC_BSRR_BR3 %1 19 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BR3 Port x reset bit y y = 0..15 : GPIOC_BSRR_BR2 %1 18 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BR2 Port x reset bit y y = 0..15 : GPIOC_BSRR_BR1 %1 17 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BR1 Port x reset bit y y = 0..15 : GPIOC_BSRR_BR0 %1 16 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BR0 Port x set bit y y= 0..15 : GPIOC_BSRR_BS15 %1 15 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BS15 Port x set bit y y= 0..15 : GPIOC_BSRR_BS14 %1 14 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BS14 Port x set bit y y= 0..15 : GPIOC_BSRR_BS13 %1 13 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BS13 Port x set bit y y= 0..15 : GPIOC_BSRR_BS12 %1 12 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BS12 Port x set bit y y= 0..15 : GPIOC_BSRR_BS11 %1 11 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BS11 Port x set bit y y= 0..15 : GPIOC_BSRR_BS10 %1 10 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BS10 Port x set bit y y= 0..15 : GPIOC_BSRR_BS9 %1 9 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BS9 Port x set bit y y= 0..15 : GPIOC_BSRR_BS8 %1 8 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BS8 Port x set bit y y= 0..15 : GPIOC_BSRR_BS7 %1 7 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BS7 Port x set bit y y= 0..15 : GPIOC_BSRR_BS6 %1 6 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BS6 Port x set bit y y= 0..15 : GPIOC_BSRR_BS5 %1 5 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BS5 Port x set bit y y= 0..15 : GPIOC_BSRR_BS4 %1 4 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BS4 Port x set bit y y= 0..15 : GPIOC_BSRR_BS3 %1 3 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BS3 Port x set bit y y= 0..15 : GPIOC_BSRR_BS2 %1 2 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BS2 Port x set bit y y= 0..15 : GPIOC_BSRR_BS1 %1 1 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BS1 Port x set bit y y= 0..15 : GPIOC_BSRR_BS0 %1 0 lshift GPIOC_BSRR bis! ; \ GPIOC_BSRR_BS0 Port x set bit y y= 0..15 \ GPIOC_LCKR (read-write) : GPIOC_LCKR_LCKK %1 16 lshift GPIOC_LCKR bis! ; \ GPIOC_LCKR_LCKK Port x lock bit y : GPIOC_LCKR_LCK15 %1 15 lshift GPIOC_LCKR bis! ; \ GPIOC_LCKR_LCK15 Port x lock bit y y= 0..15 : GPIOC_LCKR_LCK14 %1 14 lshift GPIOC_LCKR bis! ; \ GPIOC_LCKR_LCK14 Port x lock bit y y= 0..15 : GPIOC_LCKR_LCK13 %1 13 lshift GPIOC_LCKR bis! ; \ GPIOC_LCKR_LCK13 Port x lock bit y y= 0..15 : GPIOC_LCKR_LCK12 %1 12 lshift GPIOC_LCKR bis! ; \ GPIOC_LCKR_LCK12 Port x lock bit y y= 0..15 : GPIOC_LCKR_LCK11 %1 11 lshift GPIOC_LCKR bis! ; \ GPIOC_LCKR_LCK11 Port x lock bit y y= 0..15 : GPIOC_LCKR_LCK10 %1 10 lshift GPIOC_LCKR bis! ; \ GPIOC_LCKR_LCK10 Port x lock bit y y= 0..15 : GPIOC_LCKR_LCK9 %1 9 lshift GPIOC_LCKR bis! ; \ GPIOC_LCKR_LCK9 Port x lock bit y y= 0..15 : GPIOC_LCKR_LCK8 %1 8 lshift GPIOC_LCKR bis! ; \ GPIOC_LCKR_LCK8 Port x lock bit y y= 0..15 : GPIOC_LCKR_LCK7 %1 7 lshift GPIOC_LCKR bis! ; \ GPIOC_LCKR_LCK7 Port x lock bit y y= 0..15 : GPIOC_LCKR_LCK6 %1 6 lshift GPIOC_LCKR bis! ; \ GPIOC_LCKR_LCK6 Port x lock bit y y= 0..15 : GPIOC_LCKR_LCK5 %1 5 lshift GPIOC_LCKR bis! ; \ GPIOC_LCKR_LCK5 Port x lock bit y y= 0..15 : GPIOC_LCKR_LCK4 %1 4 lshift GPIOC_LCKR bis! ; \ GPIOC_LCKR_LCK4 Port x lock bit y y= 0..15 : GPIOC_LCKR_LCK3 %1 3 lshift GPIOC_LCKR bis! ; \ GPIOC_LCKR_LCK3 Port x lock bit y y= 0..15 : GPIOC_LCKR_LCK2 %1 2 lshift GPIOC_LCKR bis! ; \ GPIOC_LCKR_LCK2 Port x lock bit y y= 0..15 : GPIOC_LCKR_LCK1 %1 1 lshift GPIOC_LCKR bis! ; \ GPIOC_LCKR_LCK1 Port x lock bit y y= 0..15 : GPIOC_LCKR_LCK0 %1 0 lshift GPIOC_LCKR bis! ; \ GPIOC_LCKR_LCK0 Port x lock bit y y= 0..15 \ GPIOC_AFRL (read-write) : GPIOC_AFRL_AFRL7 ( %XXXX -- ) 28 lshift GPIOC_AFRL bis! ; \ GPIOC_AFRL_AFRL7 Alternate function selection for port x bit y y = 0..7 : GPIOC_AFRL_AFRL6 ( %XXXX -- ) 24 lshift GPIOC_AFRL bis! ; \ GPIOC_AFRL_AFRL6 Alternate function selection for port x bit y y = 0..7 : GPIOC_AFRL_AFRL5 ( %XXXX -- ) 20 lshift GPIOC_AFRL bis! ; \ GPIOC_AFRL_AFRL5 Alternate function selection for port x bit y y = 0..7 : GPIOC_AFRL_AFRL4 ( %XXXX -- ) 16 lshift GPIOC_AFRL bis! ; \ GPIOC_AFRL_AFRL4 Alternate function selection for port x bit y y = 0..7 : GPIOC_AFRL_AFRL3 ( %XXXX -- ) 12 lshift GPIOC_AFRL bis! ; \ GPIOC_AFRL_AFRL3 Alternate function selection for port x bit y y = 0..7 : GPIOC_AFRL_AFRL2 ( %XXXX -- ) 8 lshift GPIOC_AFRL bis! ; \ GPIOC_AFRL_AFRL2 Alternate function selection for port x bit y y = 0..7 : GPIOC_AFRL_AFRL1 ( %XXXX -- ) 4 lshift GPIOC_AFRL bis! ; \ GPIOC_AFRL_AFRL1 Alternate function selection for port x bit y y = 0..7 : GPIOC_AFRL_AFRL0 ( %XXXX -- ) 0 lshift GPIOC_AFRL bis! ; \ GPIOC_AFRL_AFRL0 Alternate function selection for port x bit y y = 0..7 \ GPIOC_AFRH (read-write) : GPIOC_AFRH_AFRH15 ( %XXXX -- ) 28 lshift GPIOC_AFRH bis! ; \ GPIOC_AFRH_AFRH15 Alternate function selection for port x bit y y = 8..15 : GPIOC_AFRH_AFRH14 ( %XXXX -- ) 24 lshift GPIOC_AFRH bis! ; \ GPIOC_AFRH_AFRH14 Alternate function selection for port x bit y y = 8..15 : GPIOC_AFRH_AFRH13 ( %XXXX -- ) 20 lshift GPIOC_AFRH bis! ; \ GPIOC_AFRH_AFRH13 Alternate function selection for port x bit y y = 8..15 : GPIOC_AFRH_AFRH12 ( %XXXX -- ) 16 lshift GPIOC_AFRH bis! ; \ GPIOC_AFRH_AFRH12 Alternate function selection for port x bit y y = 8..15 : GPIOC_AFRH_AFRH11 ( %XXXX -- ) 12 lshift GPIOC_AFRH bis! ; \ GPIOC_AFRH_AFRH11 Alternate function selection for port x bit y y = 8..15 : GPIOC_AFRH_AFRH10 ( %XXXX -- ) 8 lshift GPIOC_AFRH bis! ; \ GPIOC_AFRH_AFRH10 Alternate function selection for port x bit y y = 8..15 : GPIOC_AFRH_AFRH9 ( %XXXX -- ) 4 lshift GPIOC_AFRH bis! ; \ GPIOC_AFRH_AFRH9 Alternate function selection for port x bit y y = 8..15 : GPIOC_AFRH_AFRH8 ( %XXXX -- ) 0 lshift GPIOC_AFRH bis! ; \ GPIOC_AFRH_AFRH8 Alternate function selection for port x bit y y = 8..15 \ GPIOC_BRR (write-only) : GPIOC_BRR_BR0 %1 0 lshift GPIOC_BRR bis! ; \ GPIOC_BRR_BR0 Port x Reset bit y : GPIOC_BRR_BR1 %1 1 lshift GPIOC_BRR bis! ; \ GPIOC_BRR_BR1 Port x Reset bit y : GPIOC_BRR_BR2 %1 2 lshift GPIOC_BRR bis! ; \ GPIOC_BRR_BR2 Port x Reset bit y : GPIOC_BRR_BR3 %1 3 lshift GPIOC_BRR bis! ; \ GPIOC_BRR_BR3 Port x Reset bit y : GPIOC_BRR_BR4 %1 4 lshift GPIOC_BRR bis! ; \ GPIOC_BRR_BR4 Port x Reset bit y : GPIOC_BRR_BR5 %1 5 lshift GPIOC_BRR bis! ; \ GPIOC_BRR_BR5 Port x Reset bit y : GPIOC_BRR_BR6 %1 6 lshift GPIOC_BRR bis! ; \ GPIOC_BRR_BR6 Port x Reset bit y : GPIOC_BRR_BR7 %1 7 lshift GPIOC_BRR bis! ; \ GPIOC_BRR_BR7 Port x Reset bit y : GPIOC_BRR_BR8 %1 8 lshift GPIOC_BRR bis! ; \ GPIOC_BRR_BR8 Port x Reset bit y : GPIOC_BRR_BR9 %1 9 lshift GPIOC_BRR bis! ; \ GPIOC_BRR_BR9 Port x Reset bit y : GPIOC_BRR_BR10 %1 10 lshift GPIOC_BRR bis! ; \ GPIOC_BRR_BR10 Port x Reset bit y : GPIOC_BRR_BR11 %1 11 lshift GPIOC_BRR bis! ; \ GPIOC_BRR_BR11 Port x Reset bit y : GPIOC_BRR_BR12 %1 12 lshift GPIOC_BRR bis! ; \ GPIOC_BRR_BR12 Port x Reset bit y : GPIOC_BRR_BR13 %1 13 lshift GPIOC_BRR bis! ; \ GPIOC_BRR_BR13 Port x Reset bit y : GPIOC_BRR_BR14 %1 14 lshift GPIOC_BRR bis! ; \ GPIOC_BRR_BR14 Port x Reset bit y : GPIOC_BRR_BR15 %1 15 lshift GPIOC_BRR bis! ; \ GPIOC_BRR_BR15 Port x Reset bit y \ GPIOB_MODER (read-write) : GPIOB_MODER_MODER15 ( %XX -- ) 30 lshift GPIOB_MODER bis! ; \ GPIOB_MODER_MODER15 Port x configuration bits y = 0..15 : GPIOB_MODER_MODER14 ( %XX -- ) 28 lshift GPIOB_MODER bis! ; \ GPIOB_MODER_MODER14 Port x configuration bits y = 0..15 : GPIOB_MODER_MODER13 ( %XX -- ) 26 lshift GPIOB_MODER bis! ; \ GPIOB_MODER_MODER13 Port x configuration bits y = 0..15 : GPIOB_MODER_MODER12 ( %XX -- ) 24 lshift GPIOB_MODER bis! ; \ GPIOB_MODER_MODER12 Port x configuration bits y = 0..15 : GPIOB_MODER_MODER11 ( %XX -- ) 22 lshift GPIOB_MODER bis! ; \ GPIOB_MODER_MODER11 Port x configuration bits y = 0..15 : GPIOB_MODER_MODER10 ( %XX -- ) 20 lshift GPIOB_MODER bis! ; \ GPIOB_MODER_MODER10 Port x configuration bits y = 0..15 : GPIOB_MODER_MODER9 ( %XX -- ) 18 lshift GPIOB_MODER bis! ; \ GPIOB_MODER_MODER9 Port x configuration bits y = 0..15 : GPIOB_MODER_MODER8 ( %XX -- ) 16 lshift GPIOB_MODER bis! ; \ GPIOB_MODER_MODER8 Port x configuration bits y = 0..15 : GPIOB_MODER_MODER7 ( %XX -- ) 14 lshift GPIOB_MODER bis! ; \ GPIOB_MODER_MODER7 Port x configuration bits y = 0..15 : GPIOB_MODER_MODER6 ( %XX -- ) 12 lshift GPIOB_MODER bis! ; \ GPIOB_MODER_MODER6 Port x configuration bits y = 0..15 : GPIOB_MODER_MODER5 ( %XX -- ) 10 lshift GPIOB_MODER bis! ; \ GPIOB_MODER_MODER5 Port x configuration bits y = 0..15 : GPIOB_MODER_MODER4 ( %XX -- ) 8 lshift GPIOB_MODER bis! ; \ GPIOB_MODER_MODER4 Port x configuration bits y = 0..15 : GPIOB_MODER_MODER3 ( %XX -- ) 6 lshift GPIOB_MODER bis! ; \ GPIOB_MODER_MODER3 Port x configuration bits y = 0..15 : GPIOB_MODER_MODER2 ( %XX -- ) 4 lshift GPIOB_MODER bis! ; \ GPIOB_MODER_MODER2 Port x configuration bits y = 0..15 : GPIOB_MODER_MODER1 ( %XX -- ) 2 lshift GPIOB_MODER bis! ; \ GPIOB_MODER_MODER1 Port x configuration bits y = 0..15 : GPIOB_MODER_MODER0 ( %XX -- ) 0 lshift GPIOB_MODER bis! ; \ GPIOB_MODER_MODER0 Port x configuration bits y = 0..15 \ GPIOB_OTYPER (read-write) : GPIOB_OTYPER_OT15 %1 15 lshift GPIOB_OTYPER bis! ; \ GPIOB_OTYPER_OT15 Port x configuration bit 15 : GPIOB_OTYPER_OT14 %1 14 lshift GPIOB_OTYPER bis! ; \ GPIOB_OTYPER_OT14 Port x configuration bit 14 : GPIOB_OTYPER_OT13 %1 13 lshift GPIOB_OTYPER bis! ; \ GPIOB_OTYPER_OT13 Port x configuration bit 13 : GPIOB_OTYPER_OT12 %1 12 lshift GPIOB_OTYPER bis! ; \ GPIOB_OTYPER_OT12 Port x configuration bit 12 : GPIOB_OTYPER_OT11 %1 11 lshift GPIOB_OTYPER bis! ; \ GPIOB_OTYPER_OT11 Port x configuration bit 11 : GPIOB_OTYPER_OT10 %1 10 lshift GPIOB_OTYPER bis! ; \ GPIOB_OTYPER_OT10 Port x configuration bit 10 : GPIOB_OTYPER_OT9 %1 9 lshift GPIOB_OTYPER bis! ; \ GPIOB_OTYPER_OT9 Port x configuration bit 9 : GPIOB_OTYPER_OT8 %1 8 lshift GPIOB_OTYPER bis! ; \ GPIOB_OTYPER_OT8 Port x configuration bit 8 : GPIOB_OTYPER_OT7 %1 7 lshift GPIOB_OTYPER bis! ; \ GPIOB_OTYPER_OT7 Port x configuration bit 7 : GPIOB_OTYPER_OT6 %1 6 lshift GPIOB_OTYPER bis! ; \ GPIOB_OTYPER_OT6 Port x configuration bit 6 : GPIOB_OTYPER_OT5 %1 5 lshift GPIOB_OTYPER bis! ; \ GPIOB_OTYPER_OT5 Port x configuration bit 5 : GPIOB_OTYPER_OT4 %1 4 lshift GPIOB_OTYPER bis! ; \ GPIOB_OTYPER_OT4 Port x configuration bit 4 : GPIOB_OTYPER_OT3 %1 3 lshift GPIOB_OTYPER bis! ; \ GPIOB_OTYPER_OT3 Port x configuration bit 3 : GPIOB_OTYPER_OT2 %1 2 lshift GPIOB_OTYPER bis! ; \ GPIOB_OTYPER_OT2 Port x configuration bit 2 : GPIOB_OTYPER_OT1 %1 1 lshift GPIOB_OTYPER bis! ; \ GPIOB_OTYPER_OT1 Port x configuration bit 1 : GPIOB_OTYPER_OT0 %1 0 lshift GPIOB_OTYPER bis! ; \ GPIOB_OTYPER_OT0 Port x configuration bit 0 \ GPIOB_OSPEEDR (read-write) : GPIOB_OSPEEDR_OSPEEDR15 ( %XX -- ) 30 lshift GPIOB_OSPEEDR bis! ; \ GPIOB_OSPEEDR_OSPEEDR15 Port x configuration bits y = 0..15 : GPIOB_OSPEEDR_OSPEEDR14 ( %XX -- ) 28 lshift GPIOB_OSPEEDR bis! ; \ GPIOB_OSPEEDR_OSPEEDR14 Port x configuration bits y = 0..15 : GPIOB_OSPEEDR_OSPEEDR13 ( %XX -- ) 26 lshift GPIOB_OSPEEDR bis! ; \ GPIOB_OSPEEDR_OSPEEDR13 Port x configuration bits y = 0..15 : GPIOB_OSPEEDR_OSPEEDR12 ( %XX -- ) 24 lshift GPIOB_OSPEEDR bis! ; \ GPIOB_OSPEEDR_OSPEEDR12 Port x configuration bits y = 0..15 : GPIOB_OSPEEDR_OSPEEDR11 ( %XX -- ) 22 lshift GPIOB_OSPEEDR bis! ; \ GPIOB_OSPEEDR_OSPEEDR11 Port x configuration bits y = 0..15 : GPIOB_OSPEEDR_OSPEEDR10 ( %XX -- ) 20 lshift GPIOB_OSPEEDR bis! ; \ GPIOB_OSPEEDR_OSPEEDR10 Port x configuration bits y = 0..15 : GPIOB_OSPEEDR_OSPEEDR9 ( %XX -- ) 18 lshift GPIOB_OSPEEDR bis! ; \ GPIOB_OSPEEDR_OSPEEDR9 Port x configuration bits y = 0..15 : GPIOB_OSPEEDR_OSPEEDR8 ( %XX -- ) 16 lshift GPIOB_OSPEEDR bis! ; \ GPIOB_OSPEEDR_OSPEEDR8 Port x configuration bits y = 0..15 : GPIOB_OSPEEDR_OSPEEDR7 ( %XX -- ) 14 lshift GPIOB_OSPEEDR bis! ; \ GPIOB_OSPEEDR_OSPEEDR7 Port x configuration bits y = 0..15 : GPIOB_OSPEEDR_OSPEEDR6 ( %XX -- ) 12 lshift GPIOB_OSPEEDR bis! ; \ GPIOB_OSPEEDR_OSPEEDR6 Port x configuration bits y = 0..15 : GPIOB_OSPEEDR_OSPEEDR5 ( %XX -- ) 10 lshift GPIOB_OSPEEDR bis! ; \ GPIOB_OSPEEDR_OSPEEDR5 Port x configuration bits y = 0..15 : GPIOB_OSPEEDR_OSPEEDR4 ( %XX -- ) 8 lshift GPIOB_OSPEEDR bis! ; \ GPIOB_OSPEEDR_OSPEEDR4 Port x configuration bits y = 0..15 : GPIOB_OSPEEDR_OSPEEDR3 ( %XX -- ) 6 lshift GPIOB_OSPEEDR bis! ; \ GPIOB_OSPEEDR_OSPEEDR3 Port x configuration bits y = 0..15 : GPIOB_OSPEEDR_OSPEEDR2 ( %XX -- ) 4 lshift GPIOB_OSPEEDR bis! ; \ GPIOB_OSPEEDR_OSPEEDR2 Port x configuration bits y = 0..15 : GPIOB_OSPEEDR_OSPEEDR1 ( %XX -- ) 2 lshift GPIOB_OSPEEDR bis! ; \ GPIOB_OSPEEDR_OSPEEDR1 Port x configuration bits y = 0..15 : GPIOB_OSPEEDR_OSPEEDR0 ( %XX -- ) 0 lshift GPIOB_OSPEEDR bis! ; \ GPIOB_OSPEEDR_OSPEEDR0 Port x configuration bits y = 0..15 \ GPIOB_PUPDR (read-write) : GPIOB_PUPDR_PUPDR15 ( %XX -- ) 30 lshift GPIOB_PUPDR bis! ; \ GPIOB_PUPDR_PUPDR15 Port x configuration bits y = 0..15 : GPIOB_PUPDR_PUPDR14 ( %XX -- ) 28 lshift GPIOB_PUPDR bis! ; \ GPIOB_PUPDR_PUPDR14 Port x configuration bits y = 0..15 : GPIOB_PUPDR_PUPDR13 ( %XX -- ) 26 lshift GPIOB_PUPDR bis! ; \ GPIOB_PUPDR_PUPDR13 Port x configuration bits y = 0..15 : GPIOB_PUPDR_PUPDR12 ( %XX -- ) 24 lshift GPIOB_PUPDR bis! ; \ GPIOB_PUPDR_PUPDR12 Port x configuration bits y = 0..15 : GPIOB_PUPDR_PUPDR11 ( %XX -- ) 22 lshift GPIOB_PUPDR bis! ; \ GPIOB_PUPDR_PUPDR11 Port x configuration bits y = 0..15 : GPIOB_PUPDR_PUPDR10 ( %XX -- ) 20 lshift GPIOB_PUPDR bis! ; \ GPIOB_PUPDR_PUPDR10 Port x configuration bits y = 0..15 : GPIOB_PUPDR_PUPDR9 ( %XX -- ) 18 lshift GPIOB_PUPDR bis! ; \ GPIOB_PUPDR_PUPDR9 Port x configuration bits y = 0..15 : GPIOB_PUPDR_PUPDR8 ( %XX -- ) 16 lshift GPIOB_PUPDR bis! ; \ GPIOB_PUPDR_PUPDR8 Port x configuration bits y = 0..15 : GPIOB_PUPDR_PUPDR7 ( %XX -- ) 14 lshift GPIOB_PUPDR bis! ; \ GPIOB_PUPDR_PUPDR7 Port x configuration bits y = 0..15 : GPIOB_PUPDR_PUPDR6 ( %XX -- ) 12 lshift GPIOB_PUPDR bis! ; \ GPIOB_PUPDR_PUPDR6 Port x configuration bits y = 0..15 : GPIOB_PUPDR_PUPDR5 ( %XX -- ) 10 lshift GPIOB_PUPDR bis! ; \ GPIOB_PUPDR_PUPDR5 Port x configuration bits y = 0..15 : GPIOB_PUPDR_PUPDR4 ( %XX -- ) 8 lshift GPIOB_PUPDR bis! ; \ GPIOB_PUPDR_PUPDR4 Port x configuration bits y = 0..15 : GPIOB_PUPDR_PUPDR3 ( %XX -- ) 6 lshift GPIOB_PUPDR bis! ; \ GPIOB_PUPDR_PUPDR3 Port x configuration bits y = 0..15 : GPIOB_PUPDR_PUPDR2 ( %XX -- ) 4 lshift GPIOB_PUPDR bis! ; \ GPIOB_PUPDR_PUPDR2 Port x configuration bits y = 0..15 : GPIOB_PUPDR_PUPDR1 ( %XX -- ) 2 lshift GPIOB_PUPDR bis! ; \ GPIOB_PUPDR_PUPDR1 Port x configuration bits y = 0..15 : GPIOB_PUPDR_PUPDR0 ( %XX -- ) 0 lshift GPIOB_PUPDR bis! ; \ GPIOB_PUPDR_PUPDR0 Port x configuration bits y = 0..15 \ GPIOB_IDR (read-only) : GPIOB_IDR_IDR15 %1 15 lshift GPIOB_IDR bis! ; \ GPIOB_IDR_IDR15 Port input data y = 0..15 : GPIOB_IDR_IDR14 %1 14 lshift GPIOB_IDR bis! ; \ GPIOB_IDR_IDR14 Port input data y = 0..15 : GPIOB_IDR_IDR13 %1 13 lshift GPIOB_IDR bis! ; \ GPIOB_IDR_IDR13 Port input data y = 0..15 : GPIOB_IDR_IDR12 %1 12 lshift GPIOB_IDR bis! ; \ GPIOB_IDR_IDR12 Port input data y = 0..15 : GPIOB_IDR_IDR11 %1 11 lshift GPIOB_IDR bis! ; \ GPIOB_IDR_IDR11 Port input data y = 0..15 : GPIOB_IDR_IDR10 %1 10 lshift GPIOB_IDR bis! ; \ GPIOB_IDR_IDR10 Port input data y = 0..15 : GPIOB_IDR_IDR9 %1 9 lshift GPIOB_IDR bis! ; \ GPIOB_IDR_IDR9 Port input data y = 0..15 : GPIOB_IDR_IDR8 %1 8 lshift GPIOB_IDR bis! ; \ GPIOB_IDR_IDR8 Port input data y = 0..15 : GPIOB_IDR_IDR7 %1 7 lshift GPIOB_IDR bis! ; \ GPIOB_IDR_IDR7 Port input data y = 0..15 : GPIOB_IDR_IDR6 %1 6 lshift GPIOB_IDR bis! ; \ GPIOB_IDR_IDR6 Port input data y = 0..15 : GPIOB_IDR_IDR5 %1 5 lshift GPIOB_IDR bis! ; \ GPIOB_IDR_IDR5 Port input data y = 0..15 : GPIOB_IDR_IDR4 %1 4 lshift GPIOB_IDR bis! ; \ GPIOB_IDR_IDR4 Port input data y = 0..15 : GPIOB_IDR_IDR3 %1 3 lshift GPIOB_IDR bis! ; \ GPIOB_IDR_IDR3 Port input data y = 0..15 : GPIOB_IDR_IDR2 %1 2 lshift GPIOB_IDR bis! ; \ GPIOB_IDR_IDR2 Port input data y = 0..15 : GPIOB_IDR_IDR1 %1 1 lshift GPIOB_IDR bis! ; \ GPIOB_IDR_IDR1 Port input data y = 0..15 : GPIOB_IDR_IDR0 %1 0 lshift GPIOB_IDR bis! ; \ GPIOB_IDR_IDR0 Port input data y = 0..15 \ GPIOB_ODR (read-write) : GPIOB_ODR_ODR15 %1 15 lshift GPIOB_ODR bis! ; \ GPIOB_ODR_ODR15 Port output data y = 0..15 : GPIOB_ODR_ODR14 %1 14 lshift GPIOB_ODR bis! ; \ GPIOB_ODR_ODR14 Port output data y = 0..15 : GPIOB_ODR_ODR13 %1 13 lshift GPIOB_ODR bis! ; \ GPIOB_ODR_ODR13 Port output data y = 0..15 : GPIOB_ODR_ODR12 %1 12 lshift GPIOB_ODR bis! ; \ GPIOB_ODR_ODR12 Port output data y = 0..15 : GPIOB_ODR_ODR11 %1 11 lshift GPIOB_ODR bis! ; \ GPIOB_ODR_ODR11 Port output data y = 0..15 : GPIOB_ODR_ODR10 %1 10 lshift GPIOB_ODR bis! ; \ GPIOB_ODR_ODR10 Port output data y = 0..15 : GPIOB_ODR_ODR9 %1 9 lshift GPIOB_ODR bis! ; \ GPIOB_ODR_ODR9 Port output data y = 0..15 : GPIOB_ODR_ODR8 %1 8 lshift GPIOB_ODR bis! ; \ GPIOB_ODR_ODR8 Port output data y = 0..15 : GPIOB_ODR_ODR7 %1 7 lshift GPIOB_ODR bis! ; \ GPIOB_ODR_ODR7 Port output data y = 0..15 : GPIOB_ODR_ODR6 %1 6 lshift GPIOB_ODR bis! ; \ GPIOB_ODR_ODR6 Port output data y = 0..15 : GPIOB_ODR_ODR5 %1 5 lshift GPIOB_ODR bis! ; \ GPIOB_ODR_ODR5 Port output data y = 0..15 : GPIOB_ODR_ODR4 %1 4 lshift GPIOB_ODR bis! ; \ GPIOB_ODR_ODR4 Port output data y = 0..15 : GPIOB_ODR_ODR3 %1 3 lshift GPIOB_ODR bis! ; \ GPIOB_ODR_ODR3 Port output data y = 0..15 : GPIOB_ODR_ODR2 %1 2 lshift GPIOB_ODR bis! ; \ GPIOB_ODR_ODR2 Port output data y = 0..15 : GPIOB_ODR_ODR1 %1 1 lshift GPIOB_ODR bis! ; \ GPIOB_ODR_ODR1 Port output data y = 0..15 : GPIOB_ODR_ODR0 %1 0 lshift GPIOB_ODR bis! ; \ GPIOB_ODR_ODR0 Port output data y = 0..15 \ GPIOB_BSRR (write-only) : GPIOB_BSRR_BR15 %1 31 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BR15 Port x reset bit y y = 0..15 : GPIOB_BSRR_BR14 %1 30 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BR14 Port x reset bit y y = 0..15 : GPIOB_BSRR_BR13 %1 29 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BR13 Port x reset bit y y = 0..15 : GPIOB_BSRR_BR12 %1 28 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BR12 Port x reset bit y y = 0..15 : GPIOB_BSRR_BR11 %1 27 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BR11 Port x reset bit y y = 0..15 : GPIOB_BSRR_BR10 %1 26 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BR10 Port x reset bit y y = 0..15 : GPIOB_BSRR_BR9 %1 25 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BR9 Port x reset bit y y = 0..15 : GPIOB_BSRR_BR8 %1 24 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BR8 Port x reset bit y y = 0..15 : GPIOB_BSRR_BR7 %1 23 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BR7 Port x reset bit y y = 0..15 : GPIOB_BSRR_BR6 %1 22 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BR6 Port x reset bit y y = 0..15 : GPIOB_BSRR_BR5 %1 21 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BR5 Port x reset bit y y = 0..15 : GPIOB_BSRR_BR4 %1 20 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BR4 Port x reset bit y y = 0..15 : GPIOB_BSRR_BR3 %1 19 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BR3 Port x reset bit y y = 0..15 : GPIOB_BSRR_BR2 %1 18 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BR2 Port x reset bit y y = 0..15 : GPIOB_BSRR_BR1 %1 17 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BR1 Port x reset bit y y = 0..15 : GPIOB_BSRR_BR0 %1 16 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BR0 Port x set bit y y= 0..15 : GPIOB_BSRR_BS15 %1 15 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BS15 Port x set bit y y= 0..15 : GPIOB_BSRR_BS14 %1 14 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BS14 Port x set bit y y= 0..15 : GPIOB_BSRR_BS13 %1 13 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BS13 Port x set bit y y= 0..15 : GPIOB_BSRR_BS12 %1 12 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BS12 Port x set bit y y= 0..15 : GPIOB_BSRR_BS11 %1 11 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BS11 Port x set bit y y= 0..15 : GPIOB_BSRR_BS10 %1 10 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BS10 Port x set bit y y= 0..15 : GPIOB_BSRR_BS9 %1 9 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BS9 Port x set bit y y= 0..15 : GPIOB_BSRR_BS8 %1 8 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BS8 Port x set bit y y= 0..15 : GPIOB_BSRR_BS7 %1 7 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BS7 Port x set bit y y= 0..15 : GPIOB_BSRR_BS6 %1 6 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BS6 Port x set bit y y= 0..15 : GPIOB_BSRR_BS5 %1 5 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BS5 Port x set bit y y= 0..15 : GPIOB_BSRR_BS4 %1 4 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BS4 Port x set bit y y= 0..15 : GPIOB_BSRR_BS3 %1 3 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BS3 Port x set bit y y= 0..15 : GPIOB_BSRR_BS2 %1 2 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BS2 Port x set bit y y= 0..15 : GPIOB_BSRR_BS1 %1 1 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BS1 Port x set bit y y= 0..15 : GPIOB_BSRR_BS0 %1 0 lshift GPIOB_BSRR bis! ; \ GPIOB_BSRR_BS0 Port x set bit y y= 0..15 \ GPIOB_LCKR (read-write) : GPIOB_LCKR_LCKK %1 16 lshift GPIOB_LCKR bis! ; \ GPIOB_LCKR_LCKK Port x lock bit y : GPIOB_LCKR_LCK15 %1 15 lshift GPIOB_LCKR bis! ; \ GPIOB_LCKR_LCK15 Port x lock bit y y= 0..15 : GPIOB_LCKR_LCK14 %1 14 lshift GPIOB_LCKR bis! ; \ GPIOB_LCKR_LCK14 Port x lock bit y y= 0..15 : GPIOB_LCKR_LCK13 %1 13 lshift GPIOB_LCKR bis! ; \ GPIOB_LCKR_LCK13 Port x lock bit y y= 0..15 : GPIOB_LCKR_LCK12 %1 12 lshift GPIOB_LCKR bis! ; \ GPIOB_LCKR_LCK12 Port x lock bit y y= 0..15 : GPIOB_LCKR_LCK11 %1 11 lshift GPIOB_LCKR bis! ; \ GPIOB_LCKR_LCK11 Port x lock bit y y= 0..15 : GPIOB_LCKR_LCK10 %1 10 lshift GPIOB_LCKR bis! ; \ GPIOB_LCKR_LCK10 Port x lock bit y y= 0..15 : GPIOB_LCKR_LCK9 %1 9 lshift GPIOB_LCKR bis! ; \ GPIOB_LCKR_LCK9 Port x lock bit y y= 0..15 : GPIOB_LCKR_LCK8 %1 8 lshift GPIOB_LCKR bis! ; \ GPIOB_LCKR_LCK8 Port x lock bit y y= 0..15 : GPIOB_LCKR_LCK7 %1 7 lshift GPIOB_LCKR bis! ; \ GPIOB_LCKR_LCK7 Port x lock bit y y= 0..15 : GPIOB_LCKR_LCK6 %1 6 lshift GPIOB_LCKR bis! ; \ GPIOB_LCKR_LCK6 Port x lock bit y y= 0..15 : GPIOB_LCKR_LCK5 %1 5 lshift GPIOB_LCKR bis! ; \ GPIOB_LCKR_LCK5 Port x lock bit y y= 0..15 : GPIOB_LCKR_LCK4 %1 4 lshift GPIOB_LCKR bis! ; \ GPIOB_LCKR_LCK4 Port x lock bit y y= 0..15 : GPIOB_LCKR_LCK3 %1 3 lshift GPIOB_LCKR bis! ; \ GPIOB_LCKR_LCK3 Port x lock bit y y= 0..15 : GPIOB_LCKR_LCK2 %1 2 lshift GPIOB_LCKR bis! ; \ GPIOB_LCKR_LCK2 Port x lock bit y y= 0..15 : GPIOB_LCKR_LCK1 %1 1 lshift GPIOB_LCKR bis! ; \ GPIOB_LCKR_LCK1 Port x lock bit y y= 0..15 : GPIOB_LCKR_LCK0 %1 0 lshift GPIOB_LCKR bis! ; \ GPIOB_LCKR_LCK0 Port x lock bit y y= 0..15 \ GPIOB_AFRL (read-write) : GPIOB_AFRL_AFRL7 ( %XXXX -- ) 28 lshift GPIOB_AFRL bis! ; \ GPIOB_AFRL_AFRL7 Alternate function selection for port x bit y y = 0..7 : GPIOB_AFRL_AFRL6 ( %XXXX -- ) 24 lshift GPIOB_AFRL bis! ; \ GPIOB_AFRL_AFRL6 Alternate function selection for port x bit y y = 0..7 : GPIOB_AFRL_AFRL5 ( %XXXX -- ) 20 lshift GPIOB_AFRL bis! ; \ GPIOB_AFRL_AFRL5 Alternate function selection for port x bit y y = 0..7 : GPIOB_AFRL_AFRL4 ( %XXXX -- ) 16 lshift GPIOB_AFRL bis! ; \ GPIOB_AFRL_AFRL4 Alternate function selection for port x bit y y = 0..7 : GPIOB_AFRL_AFRL3 ( %XXXX -- ) 12 lshift GPIOB_AFRL bis! ; \ GPIOB_AFRL_AFRL3 Alternate function selection for port x bit y y = 0..7 : GPIOB_AFRL_AFRL2 ( %XXXX -- ) 8 lshift GPIOB_AFRL bis! ; \ GPIOB_AFRL_AFRL2 Alternate function selection for port x bit y y = 0..7 : GPIOB_AFRL_AFRL1 ( %XXXX -- ) 4 lshift GPIOB_AFRL bis! ; \ GPIOB_AFRL_AFRL1 Alternate function selection for port x bit y y = 0..7 : GPIOB_AFRL_AFRL0 ( %XXXX -- ) 0 lshift GPIOB_AFRL bis! ; \ GPIOB_AFRL_AFRL0 Alternate function selection for port x bit y y = 0..7 \ GPIOB_AFRH (read-write) : GPIOB_AFRH_AFRH15 ( %XXXX -- ) 28 lshift GPIOB_AFRH bis! ; \ GPIOB_AFRH_AFRH15 Alternate function selection for port x bit y y = 8..15 : GPIOB_AFRH_AFRH14 ( %XXXX -- ) 24 lshift GPIOB_AFRH bis! ; \ GPIOB_AFRH_AFRH14 Alternate function selection for port x bit y y = 8..15 : GPIOB_AFRH_AFRH13 ( %XXXX -- ) 20 lshift GPIOB_AFRH bis! ; \ GPIOB_AFRH_AFRH13 Alternate function selection for port x bit y y = 8..15 : GPIOB_AFRH_AFRH12 ( %XXXX -- ) 16 lshift GPIOB_AFRH bis! ; \ GPIOB_AFRH_AFRH12 Alternate function selection for port x bit y y = 8..15 : GPIOB_AFRH_AFRH11 ( %XXXX -- ) 12 lshift GPIOB_AFRH bis! ; \ GPIOB_AFRH_AFRH11 Alternate function selection for port x bit y y = 8..15 : GPIOB_AFRH_AFRH10 ( %XXXX -- ) 8 lshift GPIOB_AFRH bis! ; \ GPIOB_AFRH_AFRH10 Alternate function selection for port x bit y y = 8..15 : GPIOB_AFRH_AFRH9 ( %XXXX -- ) 4 lshift GPIOB_AFRH bis! ; \ GPIOB_AFRH_AFRH9 Alternate function selection for port x bit y y = 8..15 : GPIOB_AFRH_AFRH8 ( %XXXX -- ) 0 lshift GPIOB_AFRH bis! ; \ GPIOB_AFRH_AFRH8 Alternate function selection for port x bit y y = 8..15 \ GPIOB_BRR (write-only) : GPIOB_BRR_BR0 %1 0 lshift GPIOB_BRR bis! ; \ GPIOB_BRR_BR0 Port x Reset bit y : GPIOB_BRR_BR1 %1 1 lshift GPIOB_BRR bis! ; \ GPIOB_BRR_BR1 Port x Reset bit y : GPIOB_BRR_BR2 %1 2 lshift GPIOB_BRR bis! ; \ GPIOB_BRR_BR2 Port x Reset bit y : GPIOB_BRR_BR3 %1 3 lshift GPIOB_BRR bis! ; \ GPIOB_BRR_BR3 Port x Reset bit y : GPIOB_BRR_BR4 %1 4 lshift GPIOB_BRR bis! ; \ GPIOB_BRR_BR4 Port x Reset bit y : GPIOB_BRR_BR5 %1 5 lshift GPIOB_BRR bis! ; \ GPIOB_BRR_BR5 Port x Reset bit y : GPIOB_BRR_BR6 %1 6 lshift GPIOB_BRR bis! ; \ GPIOB_BRR_BR6 Port x Reset bit y : GPIOB_BRR_BR7 %1 7 lshift GPIOB_BRR bis! ; \ GPIOB_BRR_BR7 Port x Reset bit y : GPIOB_BRR_BR8 %1 8 lshift GPIOB_BRR bis! ; \ GPIOB_BRR_BR8 Port x Reset bit y : GPIOB_BRR_BR9 %1 9 lshift GPIOB_BRR bis! ; \ GPIOB_BRR_BR9 Port x Reset bit y : GPIOB_BRR_BR10 %1 10 lshift GPIOB_BRR bis! ; \ GPIOB_BRR_BR10 Port x Reset bit y : GPIOB_BRR_BR11 %1 11 lshift GPIOB_BRR bis! ; \ GPIOB_BRR_BR11 Port x Reset bit y : GPIOB_BRR_BR12 %1 12 lshift GPIOB_BRR bis! ; \ GPIOB_BRR_BR12 Port x Reset bit y : GPIOB_BRR_BR13 %1 13 lshift GPIOB_BRR bis! ; \ GPIOB_BRR_BR13 Port x Reset bit y : GPIOB_BRR_BR14 %1 14 lshift GPIOB_BRR bis! ; \ GPIOB_BRR_BR14 Port x Reset bit y : GPIOB_BRR_BR15 %1 15 lshift GPIOB_BRR bis! ; \ GPIOB_BRR_BR15 Port x Reset bit y \ GPIOA_MODER (read-write) : GPIOA_MODER_MODER15 ( %XX -- ) 30 lshift GPIOA_MODER bis! ; \ GPIOA_MODER_MODER15 Port x configuration bits y = 0..15 : GPIOA_MODER_MODER14 ( %XX -- ) 28 lshift GPIOA_MODER bis! ; \ GPIOA_MODER_MODER14 Port x configuration bits y = 0..15 : GPIOA_MODER_MODER13 ( %XX -- ) 26 lshift GPIOA_MODER bis! ; \ GPIOA_MODER_MODER13 Port x configuration bits y = 0..15 : GPIOA_MODER_MODER12 ( %XX -- ) 24 lshift GPIOA_MODER bis! ; \ GPIOA_MODER_MODER12 Port x configuration bits y = 0..15 : GPIOA_MODER_MODER11 ( %XX -- ) 22 lshift GPIOA_MODER bis! ; \ GPIOA_MODER_MODER11 Port x configuration bits y = 0..15 : GPIOA_MODER_MODER10 ( %XX -- ) 20 lshift GPIOA_MODER bis! ; \ GPIOA_MODER_MODER10 Port x configuration bits y = 0..15 : GPIOA_MODER_MODER9 ( %XX -- ) 18 lshift GPIOA_MODER bis! ; \ GPIOA_MODER_MODER9 Port x configuration bits y = 0..15 : GPIOA_MODER_MODER8 ( %XX -- ) 16 lshift GPIOA_MODER bis! ; \ GPIOA_MODER_MODER8 Port x configuration bits y = 0..15 : GPIOA_MODER_MODER7 ( %XX -- ) 14 lshift GPIOA_MODER bis! ; \ GPIOA_MODER_MODER7 Port x configuration bits y = 0..15 : GPIOA_MODER_MODER6 ( %XX -- ) 12 lshift GPIOA_MODER bis! ; \ GPIOA_MODER_MODER6 Port x configuration bits y = 0..15 : GPIOA_MODER_MODER5 ( %XX -- ) 10 lshift GPIOA_MODER bis! ; \ GPIOA_MODER_MODER5 Port x configuration bits y = 0..15 : GPIOA_MODER_MODER4 ( %XX -- ) 8 lshift GPIOA_MODER bis! ; \ GPIOA_MODER_MODER4 Port x configuration bits y = 0..15 : GPIOA_MODER_MODER3 ( %XX -- ) 6 lshift GPIOA_MODER bis! ; \ GPIOA_MODER_MODER3 Port x configuration bits y = 0..15 : GPIOA_MODER_MODER2 ( %XX -- ) 4 lshift GPIOA_MODER bis! ; \ GPIOA_MODER_MODER2 Port x configuration bits y = 0..15 : GPIOA_MODER_MODER1 ( %XX -- ) 2 lshift GPIOA_MODER bis! ; \ GPIOA_MODER_MODER1 Port x configuration bits y = 0..15 : GPIOA_MODER_MODER0 ( %XX -- ) 0 lshift GPIOA_MODER bis! ; \ GPIOA_MODER_MODER0 Port x configuration bits y = 0..15 \ GPIOA_OTYPER (read-write) : GPIOA_OTYPER_OT15 %1 15 lshift GPIOA_OTYPER bis! ; \ GPIOA_OTYPER_OT15 Port x configuration bits y = 0..15 : GPIOA_OTYPER_OT14 %1 14 lshift GPIOA_OTYPER bis! ; \ GPIOA_OTYPER_OT14 Port x configuration bits y = 0..15 : GPIOA_OTYPER_OT13 %1 13 lshift GPIOA_OTYPER bis! ; \ GPIOA_OTYPER_OT13 Port x configuration bits y = 0..15 : GPIOA_OTYPER_OT12 %1 12 lshift GPIOA_OTYPER bis! ; \ GPIOA_OTYPER_OT12 Port x configuration bits y = 0..15 : GPIOA_OTYPER_OT11 %1 11 lshift GPIOA_OTYPER bis! ; \ GPIOA_OTYPER_OT11 Port x configuration bits y = 0..15 : GPIOA_OTYPER_OT10 %1 10 lshift GPIOA_OTYPER bis! ; \ GPIOA_OTYPER_OT10 Port x configuration bits y = 0..15 : GPIOA_OTYPER_OT9 %1 9 lshift GPIOA_OTYPER bis! ; \ GPIOA_OTYPER_OT9 Port x configuration bits y = 0..15 : GPIOA_OTYPER_OT8 %1 8 lshift GPIOA_OTYPER bis! ; \ GPIOA_OTYPER_OT8 Port x configuration bits y = 0..15 : GPIOA_OTYPER_OT7 %1 7 lshift GPIOA_OTYPER bis! ; \ GPIOA_OTYPER_OT7 Port x configuration bits y = 0..15 : GPIOA_OTYPER_OT6 %1 6 lshift GPIOA_OTYPER bis! ; \ GPIOA_OTYPER_OT6 Port x configuration bits y = 0..15 : GPIOA_OTYPER_OT5 %1 5 lshift GPIOA_OTYPER bis! ; \ GPIOA_OTYPER_OT5 Port x configuration bits y = 0..15 : GPIOA_OTYPER_OT4 %1 4 lshift GPIOA_OTYPER bis! ; \ GPIOA_OTYPER_OT4 Port x configuration bits y = 0..15 : GPIOA_OTYPER_OT3 %1 3 lshift GPIOA_OTYPER bis! ; \ GPIOA_OTYPER_OT3 Port x configuration bits y = 0..15 : GPIOA_OTYPER_OT2 %1 2 lshift GPIOA_OTYPER bis! ; \ GPIOA_OTYPER_OT2 Port x configuration bits y = 0..15 : GPIOA_OTYPER_OT1 %1 1 lshift GPIOA_OTYPER bis! ; \ GPIOA_OTYPER_OT1 Port x configuration bits y = 0..15 : GPIOA_OTYPER_OT0 %1 0 lshift GPIOA_OTYPER bis! ; \ GPIOA_OTYPER_OT0 Port x configuration bits y = 0..15 \ GPIOA_OSPEEDR (read-write) : GPIOA_OSPEEDR_OSPEEDR15 ( %XX -- ) 30 lshift GPIOA_OSPEEDR bis! ; \ GPIOA_OSPEEDR_OSPEEDR15 Port x configuration bits y = 0..15 : GPIOA_OSPEEDR_OSPEEDR14 ( %XX -- ) 28 lshift GPIOA_OSPEEDR bis! ; \ GPIOA_OSPEEDR_OSPEEDR14 Port x configuration bits y = 0..15 : GPIOA_OSPEEDR_OSPEEDR13 ( %XX -- ) 26 lshift GPIOA_OSPEEDR bis! ; \ GPIOA_OSPEEDR_OSPEEDR13 Port x configuration bits y = 0..15 : GPIOA_OSPEEDR_OSPEEDR12 ( %XX -- ) 24 lshift GPIOA_OSPEEDR bis! ; \ GPIOA_OSPEEDR_OSPEEDR12 Port x configuration bits y = 0..15 : GPIOA_OSPEEDR_OSPEEDR11 ( %XX -- ) 22 lshift GPIOA_OSPEEDR bis! ; \ GPIOA_OSPEEDR_OSPEEDR11 Port x configuration bits y = 0..15 : GPIOA_OSPEEDR_OSPEEDR10 ( %XX -- ) 20 lshift GPIOA_OSPEEDR bis! ; \ GPIOA_OSPEEDR_OSPEEDR10 Port x configuration bits y = 0..15 : GPIOA_OSPEEDR_OSPEEDR9 ( %XX -- ) 18 lshift GPIOA_OSPEEDR bis! ; \ GPIOA_OSPEEDR_OSPEEDR9 Port x configuration bits y = 0..15 : GPIOA_OSPEEDR_OSPEEDR8 ( %XX -- ) 16 lshift GPIOA_OSPEEDR bis! ; \ GPIOA_OSPEEDR_OSPEEDR8 Port x configuration bits y = 0..15 : GPIOA_OSPEEDR_OSPEEDR7 ( %XX -- ) 14 lshift GPIOA_OSPEEDR bis! ; \ GPIOA_OSPEEDR_OSPEEDR7 Port x configuration bits y = 0..15 : GPIOA_OSPEEDR_OSPEEDR6 ( %XX -- ) 12 lshift GPIOA_OSPEEDR bis! ; \ GPIOA_OSPEEDR_OSPEEDR6 Port x configuration bits y = 0..15 : GPIOA_OSPEEDR_OSPEEDR5 ( %XX -- ) 10 lshift GPIOA_OSPEEDR bis! ; \ GPIOA_OSPEEDR_OSPEEDR5 Port x configuration bits y = 0..15 : GPIOA_OSPEEDR_OSPEEDR4 ( %XX -- ) 8 lshift GPIOA_OSPEEDR bis! ; \ GPIOA_OSPEEDR_OSPEEDR4 Port x configuration bits y = 0..15 : GPIOA_OSPEEDR_OSPEEDR3 ( %XX -- ) 6 lshift GPIOA_OSPEEDR bis! ; \ GPIOA_OSPEEDR_OSPEEDR3 Port x configuration bits y = 0..15 : GPIOA_OSPEEDR_OSPEEDR2 ( %XX -- ) 4 lshift GPIOA_OSPEEDR bis! ; \ GPIOA_OSPEEDR_OSPEEDR2 Port x configuration bits y = 0..15 : GPIOA_OSPEEDR_OSPEEDR1 ( %XX -- ) 2 lshift GPIOA_OSPEEDR bis! ; \ GPIOA_OSPEEDR_OSPEEDR1 Port x configuration bits y = 0..15 : GPIOA_OSPEEDR_OSPEEDR0 ( %XX -- ) 0 lshift GPIOA_OSPEEDR bis! ; \ GPIOA_OSPEEDR_OSPEEDR0 Port x configuration bits y = 0..15 \ GPIOA_PUPDR (read-write) : GPIOA_PUPDR_PUPDR15 ( %XX -- ) 30 lshift GPIOA_PUPDR bis! ; \ GPIOA_PUPDR_PUPDR15 Port x configuration bits y = 0..15 : GPIOA_PUPDR_PUPDR14 ( %XX -- ) 28 lshift GPIOA_PUPDR bis! ; \ GPIOA_PUPDR_PUPDR14 Port x configuration bits y = 0..15 : GPIOA_PUPDR_PUPDR13 ( %XX -- ) 26 lshift GPIOA_PUPDR bis! ; \ GPIOA_PUPDR_PUPDR13 Port x configuration bits y = 0..15 : GPIOA_PUPDR_PUPDR12 ( %XX -- ) 24 lshift GPIOA_PUPDR bis! ; \ GPIOA_PUPDR_PUPDR12 Port x configuration bits y = 0..15 : GPIOA_PUPDR_PUPDR11 ( %XX -- ) 22 lshift GPIOA_PUPDR bis! ; \ GPIOA_PUPDR_PUPDR11 Port x configuration bits y = 0..15 : GPIOA_PUPDR_PUPDR10 ( %XX -- ) 20 lshift GPIOA_PUPDR bis! ; \ GPIOA_PUPDR_PUPDR10 Port x configuration bits y = 0..15 : GPIOA_PUPDR_PUPDR9 ( %XX -- ) 18 lshift GPIOA_PUPDR bis! ; \ GPIOA_PUPDR_PUPDR9 Port x configuration bits y = 0..15 : GPIOA_PUPDR_PUPDR8 ( %XX -- ) 16 lshift GPIOA_PUPDR bis! ; \ GPIOA_PUPDR_PUPDR8 Port x configuration bits y = 0..15 : GPIOA_PUPDR_PUPDR7 ( %XX -- ) 14 lshift GPIOA_PUPDR bis! ; \ GPIOA_PUPDR_PUPDR7 Port x configuration bits y = 0..15 : GPIOA_PUPDR_PUPDR6 ( %XX -- ) 12 lshift GPIOA_PUPDR bis! ; \ GPIOA_PUPDR_PUPDR6 Port x configuration bits y = 0..15 : GPIOA_PUPDR_PUPDR5 ( %XX -- ) 10 lshift GPIOA_PUPDR bis! ; \ GPIOA_PUPDR_PUPDR5 Port x configuration bits y = 0..15 : GPIOA_PUPDR_PUPDR4 ( %XX -- ) 8 lshift GPIOA_PUPDR bis! ; \ GPIOA_PUPDR_PUPDR4 Port x configuration bits y = 0..15 : GPIOA_PUPDR_PUPDR3 ( %XX -- ) 6 lshift GPIOA_PUPDR bis! ; \ GPIOA_PUPDR_PUPDR3 Port x configuration bits y = 0..15 : GPIOA_PUPDR_PUPDR2 ( %XX -- ) 4 lshift GPIOA_PUPDR bis! ; \ GPIOA_PUPDR_PUPDR2 Port x configuration bits y = 0..15 : GPIOA_PUPDR_PUPDR1 ( %XX -- ) 2 lshift GPIOA_PUPDR bis! ; \ GPIOA_PUPDR_PUPDR1 Port x configuration bits y = 0..15 : GPIOA_PUPDR_PUPDR0 ( %XX -- ) 0 lshift GPIOA_PUPDR bis! ; \ GPIOA_PUPDR_PUPDR0 Port x configuration bits y = 0..15 \ GPIOA_IDR (read-only) : GPIOA_IDR_IDR15 %1 15 lshift GPIOA_IDR bis! ; \ GPIOA_IDR_IDR15 Port input data y = 0..15 : GPIOA_IDR_IDR14 %1 14 lshift GPIOA_IDR bis! ; \ GPIOA_IDR_IDR14 Port input data y = 0..15 : GPIOA_IDR_IDR13 %1 13 lshift GPIOA_IDR bis! ; \ GPIOA_IDR_IDR13 Port input data y = 0..15 : GPIOA_IDR_IDR12 %1 12 lshift GPIOA_IDR bis! ; \ GPIOA_IDR_IDR12 Port input data y = 0..15 : GPIOA_IDR_IDR11 %1 11 lshift GPIOA_IDR bis! ; \ GPIOA_IDR_IDR11 Port input data y = 0..15 : GPIOA_IDR_IDR10 %1 10 lshift GPIOA_IDR bis! ; \ GPIOA_IDR_IDR10 Port input data y = 0..15 : GPIOA_IDR_IDR9 %1 9 lshift GPIOA_IDR bis! ; \ GPIOA_IDR_IDR9 Port input data y = 0..15 : GPIOA_IDR_IDR8 %1 8 lshift GPIOA_IDR bis! ; \ GPIOA_IDR_IDR8 Port input data y = 0..15 : GPIOA_IDR_IDR7 %1 7 lshift GPIOA_IDR bis! ; \ GPIOA_IDR_IDR7 Port input data y = 0..15 : GPIOA_IDR_IDR6 %1 6 lshift GPIOA_IDR bis! ; \ GPIOA_IDR_IDR6 Port input data y = 0..15 : GPIOA_IDR_IDR5 %1 5 lshift GPIOA_IDR bis! ; \ GPIOA_IDR_IDR5 Port input data y = 0..15 : GPIOA_IDR_IDR4 %1 4 lshift GPIOA_IDR bis! ; \ GPIOA_IDR_IDR4 Port input data y = 0..15 : GPIOA_IDR_IDR3 %1 3 lshift GPIOA_IDR bis! ; \ GPIOA_IDR_IDR3 Port input data y = 0..15 : GPIOA_IDR_IDR2 %1 2 lshift GPIOA_IDR bis! ; \ GPIOA_IDR_IDR2 Port input data y = 0..15 : GPIOA_IDR_IDR1 %1 1 lshift GPIOA_IDR bis! ; \ GPIOA_IDR_IDR1 Port input data y = 0..15 : GPIOA_IDR_IDR0 %1 0 lshift GPIOA_IDR bis! ; \ GPIOA_IDR_IDR0 Port input data y = 0..15 \ GPIOA_ODR (read-write) : GPIOA_ODR_ODR15 %1 15 lshift GPIOA_ODR bis! ; \ GPIOA_ODR_ODR15 Port output data y = 0..15 : GPIOA_ODR_ODR14 %1 14 lshift GPIOA_ODR bis! ; \ GPIOA_ODR_ODR14 Port output data y = 0..15 : GPIOA_ODR_ODR13 %1 13 lshift GPIOA_ODR bis! ; \ GPIOA_ODR_ODR13 Port output data y = 0..15 : GPIOA_ODR_ODR12 %1 12 lshift GPIOA_ODR bis! ; \ GPIOA_ODR_ODR12 Port output data y = 0..15 : GPIOA_ODR_ODR11 %1 11 lshift GPIOA_ODR bis! ; \ GPIOA_ODR_ODR11 Port output data y = 0..15 : GPIOA_ODR_ODR10 %1 10 lshift GPIOA_ODR bis! ; \ GPIOA_ODR_ODR10 Port output data y = 0..15 : GPIOA_ODR_ODR9 %1 9 lshift GPIOA_ODR bis! ; \ GPIOA_ODR_ODR9 Port output data y = 0..15 : GPIOA_ODR_ODR8 %1 8 lshift GPIOA_ODR bis! ; \ GPIOA_ODR_ODR8 Port output data y = 0..15 : GPIOA_ODR_ODR7 %1 7 lshift GPIOA_ODR bis! ; \ GPIOA_ODR_ODR7 Port output data y = 0..15 : GPIOA_ODR_ODR6 %1 6 lshift GPIOA_ODR bis! ; \ GPIOA_ODR_ODR6 Port output data y = 0..15 : GPIOA_ODR_ODR5 %1 5 lshift GPIOA_ODR bis! ; \ GPIOA_ODR_ODR5 Port output data y = 0..15 : GPIOA_ODR_ODR4 %1 4 lshift GPIOA_ODR bis! ; \ GPIOA_ODR_ODR4 Port output data y = 0..15 : GPIOA_ODR_ODR3 %1 3 lshift GPIOA_ODR bis! ; \ GPIOA_ODR_ODR3 Port output data y = 0..15 : GPIOA_ODR_ODR2 %1 2 lshift GPIOA_ODR bis! ; \ GPIOA_ODR_ODR2 Port output data y = 0..15 : GPIOA_ODR_ODR1 %1 1 lshift GPIOA_ODR bis! ; \ GPIOA_ODR_ODR1 Port output data y = 0..15 : GPIOA_ODR_ODR0 %1 0 lshift GPIOA_ODR bis! ; \ GPIOA_ODR_ODR0 Port output data y = 0..15 \ GPIOA_BSRR (write-only) : GPIOA_BSRR_BR15 %1 31 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BR15 Port x reset bit y y = 0..15 : GPIOA_BSRR_BR14 %1 30 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BR14 Port x reset bit y y = 0..15 : GPIOA_BSRR_BR13 %1 29 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BR13 Port x reset bit y y = 0..15 : GPIOA_BSRR_BR12 %1 28 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BR12 Port x reset bit y y = 0..15 : GPIOA_BSRR_BR11 %1 27 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BR11 Port x reset bit y y = 0..15 : GPIOA_BSRR_BR10 %1 26 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BR10 Port x reset bit y y = 0..15 : GPIOA_BSRR_BR9 %1 25 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BR9 Port x reset bit y y = 0..15 : GPIOA_BSRR_BR8 %1 24 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BR8 Port x reset bit y y = 0..15 : GPIOA_BSRR_BR7 %1 23 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BR7 Port x reset bit y y = 0..15 : GPIOA_BSRR_BR6 %1 22 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BR6 Port x reset bit y y = 0..15 : GPIOA_BSRR_BR5 %1 21 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BR5 Port x reset bit y y = 0..15 : GPIOA_BSRR_BR4 %1 20 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BR4 Port x reset bit y y = 0..15 : GPIOA_BSRR_BR3 %1 19 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BR3 Port x reset bit y y = 0..15 : GPIOA_BSRR_BR2 %1 18 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BR2 Port x reset bit y y = 0..15 : GPIOA_BSRR_BR1 %1 17 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BR1 Port x reset bit y y = 0..15 : GPIOA_BSRR_BR0 %1 16 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BR0 Port x set bit y y= 0..15 : GPIOA_BSRR_BS15 %1 15 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BS15 Port x set bit y y= 0..15 : GPIOA_BSRR_BS14 %1 14 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BS14 Port x set bit y y= 0..15 : GPIOA_BSRR_BS13 %1 13 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BS13 Port x set bit y y= 0..15 : GPIOA_BSRR_BS12 %1 12 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BS12 Port x set bit y y= 0..15 : GPIOA_BSRR_BS11 %1 11 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BS11 Port x set bit y y= 0..15 : GPIOA_BSRR_BS10 %1 10 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BS10 Port x set bit y y= 0..15 : GPIOA_BSRR_BS9 %1 9 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BS9 Port x set bit y y= 0..15 : GPIOA_BSRR_BS8 %1 8 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BS8 Port x set bit y y= 0..15 : GPIOA_BSRR_BS7 %1 7 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BS7 Port x set bit y y= 0..15 : GPIOA_BSRR_BS6 %1 6 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BS6 Port x set bit y y= 0..15 : GPIOA_BSRR_BS5 %1 5 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BS5 Port x set bit y y= 0..15 : GPIOA_BSRR_BS4 %1 4 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BS4 Port x set bit y y= 0..15 : GPIOA_BSRR_BS3 %1 3 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BS3 Port x set bit y y= 0..15 : GPIOA_BSRR_BS2 %1 2 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BS2 Port x set bit y y= 0..15 : GPIOA_BSRR_BS1 %1 1 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BS1 Port x set bit y y= 0..15 : GPIOA_BSRR_BS0 %1 0 lshift GPIOA_BSRR bis! ; \ GPIOA_BSRR_BS0 Port x set bit y y= 0..15 \ GPIOA_LCKR (read-write) : GPIOA_LCKR_LCKK %1 16 lshift GPIOA_LCKR bis! ; \ GPIOA_LCKR_LCKK Port x lock bit y y= 0..15 : GPIOA_LCKR_LCK15 %1 15 lshift GPIOA_LCKR bis! ; \ GPIOA_LCKR_LCK15 Port x lock bit y y= 0..15 : GPIOA_LCKR_LCK14 %1 14 lshift GPIOA_LCKR bis! ; \ GPIOA_LCKR_LCK14 Port x lock bit y y= 0..15 : GPIOA_LCKR_LCK13 %1 13 lshift GPIOA_LCKR bis! ; \ GPIOA_LCKR_LCK13 Port x lock bit y y= 0..15 : GPIOA_LCKR_LCK12 %1 12 lshift GPIOA_LCKR bis! ; \ GPIOA_LCKR_LCK12 Port x lock bit y y= 0..15 : GPIOA_LCKR_LCK11 %1 11 lshift GPIOA_LCKR bis! ; \ GPIOA_LCKR_LCK11 Port x lock bit y y= 0..15 : GPIOA_LCKR_LCK10 %1 10 lshift GPIOA_LCKR bis! ; \ GPIOA_LCKR_LCK10 Port x lock bit y y= 0..15 : GPIOA_LCKR_LCK9 %1 9 lshift GPIOA_LCKR bis! ; \ GPIOA_LCKR_LCK9 Port x lock bit y y= 0..15 : GPIOA_LCKR_LCK8 %1 8 lshift GPIOA_LCKR bis! ; \ GPIOA_LCKR_LCK8 Port x lock bit y y= 0..15 : GPIOA_LCKR_LCK7 %1 7 lshift GPIOA_LCKR bis! ; \ GPIOA_LCKR_LCK7 Port x lock bit y y= 0..15 : GPIOA_LCKR_LCK6 %1 6 lshift GPIOA_LCKR bis! ; \ GPIOA_LCKR_LCK6 Port x lock bit y y= 0..15 : GPIOA_LCKR_LCK5 %1 5 lshift GPIOA_LCKR bis! ; \ GPIOA_LCKR_LCK5 Port x lock bit y y= 0..15 : GPIOA_LCKR_LCK4 %1 4 lshift GPIOA_LCKR bis! ; \ GPIOA_LCKR_LCK4 Port x lock bit y y= 0..15 : GPIOA_LCKR_LCK3 %1 3 lshift GPIOA_LCKR bis! ; \ GPIOA_LCKR_LCK3 Port x lock bit y y= 0..15 : GPIOA_LCKR_LCK2 %1 2 lshift GPIOA_LCKR bis! ; \ GPIOA_LCKR_LCK2 Port x lock bit y y= 0..15 : GPIOA_LCKR_LCK1 %1 1 lshift GPIOA_LCKR bis! ; \ GPIOA_LCKR_LCK1 Port x lock bit y y= 0..15 : GPIOA_LCKR_LCK0 %1 0 lshift GPIOA_LCKR bis! ; \ GPIOA_LCKR_LCK0 Port x lock bit y y= 0..15 \ GPIOA_AFRL (read-write) : GPIOA_AFRL_AFRL7 ( %XXXX -- ) 28 lshift GPIOA_AFRL bis! ; \ GPIOA_AFRL_AFRL7 Alternate function selection for port x bit y y = 0..7 : GPIOA_AFRL_AFRL6 ( %XXXX -- ) 24 lshift GPIOA_AFRL bis! ; \ GPIOA_AFRL_AFRL6 Alternate function selection for port x bit y y = 0..7 : GPIOA_AFRL_AFRL5 ( %XXXX -- ) 20 lshift GPIOA_AFRL bis! ; \ GPIOA_AFRL_AFRL5 Alternate function selection for port x bit y y = 0..7 : GPIOA_AFRL_AFRL4 ( %XXXX -- ) 16 lshift GPIOA_AFRL bis! ; \ GPIOA_AFRL_AFRL4 Alternate function selection for port x bit y y = 0..7 : GPIOA_AFRL_AFRL3 ( %XXXX -- ) 12 lshift GPIOA_AFRL bis! ; \ GPIOA_AFRL_AFRL3 Alternate function selection for port x bit y y = 0..7 : GPIOA_AFRL_AFRL2 ( %XXXX -- ) 8 lshift GPIOA_AFRL bis! ; \ GPIOA_AFRL_AFRL2 Alternate function selection for port x bit y y = 0..7 : GPIOA_AFRL_AFRL1 ( %XXXX -- ) 4 lshift GPIOA_AFRL bis! ; \ GPIOA_AFRL_AFRL1 Alternate function selection for port x bit y y = 0..7 : GPIOA_AFRL_AFRL0 ( %XXXX -- ) 0 lshift GPIOA_AFRL bis! ; \ GPIOA_AFRL_AFRL0 Alternate function selection for port x bit y y = 0..7 \ GPIOA_AFRH (read-write) : GPIOA_AFRH_AFRH15 ( %XXXX -- ) 28 lshift GPIOA_AFRH bis! ; \ GPIOA_AFRH_AFRH15 Alternate function selection for port x bit y y = 8..15 : GPIOA_AFRH_AFRH14 ( %XXXX -- ) 24 lshift GPIOA_AFRH bis! ; \ GPIOA_AFRH_AFRH14 Alternate function selection for port x bit y y = 8..15 : GPIOA_AFRH_AFRH13 ( %XXXX -- ) 20 lshift GPIOA_AFRH bis! ; \ GPIOA_AFRH_AFRH13 Alternate function selection for port x bit y y = 8..15 : GPIOA_AFRH_AFRH12 ( %XXXX -- ) 16 lshift GPIOA_AFRH bis! ; \ GPIOA_AFRH_AFRH12 Alternate function selection for port x bit y y = 8..15 : GPIOA_AFRH_AFRH11 ( %XXXX -- ) 12 lshift GPIOA_AFRH bis! ; \ GPIOA_AFRH_AFRH11 Alternate function selection for port x bit y y = 8..15 : GPIOA_AFRH_AFRH10 ( %XXXX -- ) 8 lshift GPIOA_AFRH bis! ; \ GPIOA_AFRH_AFRH10 Alternate function selection for port x bit y y = 8..15 : GPIOA_AFRH_AFRH9 ( %XXXX -- ) 4 lshift GPIOA_AFRH bis! ; \ GPIOA_AFRH_AFRH9 Alternate function selection for port x bit y y = 8..15 : GPIOA_AFRH_AFRH8 ( %XXXX -- ) 0 lshift GPIOA_AFRH bis! ; \ GPIOA_AFRH_AFRH8 Alternate function selection for port x bit y y = 8..15 \ GPIOA_BRR (write-only) : GPIOA_BRR_BR0 %1 0 lshift GPIOA_BRR bis! ; \ GPIOA_BRR_BR0 Port x Reset bit y : GPIOA_BRR_BR1 %1 1 lshift GPIOA_BRR bis! ; \ GPIOA_BRR_BR1 Port x Reset bit y : GPIOA_BRR_BR2 %1 2 lshift GPIOA_BRR bis! ; \ GPIOA_BRR_BR2 Port x Reset bit y : GPIOA_BRR_BR3 %1 3 lshift GPIOA_BRR bis! ; \ GPIOA_BRR_BR3 Port x Reset bit y : GPIOA_BRR_BR4 %1 4 lshift GPIOA_BRR bis! ; \ GPIOA_BRR_BR4 Port x Reset bit y : GPIOA_BRR_BR5 %1 5 lshift GPIOA_BRR bis! ; \ GPIOA_BRR_BR5 Port x Reset bit y : GPIOA_BRR_BR6 %1 6 lshift GPIOA_BRR bis! ; \ GPIOA_BRR_BR6 Port x Reset bit y : GPIOA_BRR_BR7 %1 7 lshift GPIOA_BRR bis! ; \ GPIOA_BRR_BR7 Port x Reset bit y : GPIOA_BRR_BR8 %1 8 lshift GPIOA_BRR bis! ; \ GPIOA_BRR_BR8 Port x Reset bit y : GPIOA_BRR_BR9 %1 9 lshift GPIOA_BRR bis! ; \ GPIOA_BRR_BR9 Port x Reset bit y : GPIOA_BRR_BR10 %1 10 lshift GPIOA_BRR bis! ; \ GPIOA_BRR_BR10 Port x Reset bit y : GPIOA_BRR_BR11 %1 11 lshift GPIOA_BRR bis! ; \ GPIOA_BRR_BR11 Port x Reset bit y : GPIOA_BRR_BR12 %1 12 lshift GPIOA_BRR bis! ; \ GPIOA_BRR_BR12 Port x Reset bit y : GPIOA_BRR_BR13 %1 13 lshift GPIOA_BRR bis! ; \ GPIOA_BRR_BR13 Port x Reset bit y : GPIOA_BRR_BR14 %1 14 lshift GPIOA_BRR bis! ; \ GPIOA_BRR_BR14 Port x Reset bit y : GPIOA_BRR_BR15 %1 15 lshift GPIOA_BRR bis! ; \ GPIOA_BRR_BR15 Port x Reset bit y \ TIM6_CR1 (read-write) : TIM6_CR1_ARPE %1 7 lshift TIM6_CR1 bis! ; \ TIM6_CR1_ARPE Auto-reload preload enable : TIM6_CR1_OPM %1 3 lshift TIM6_CR1 bis! ; \ TIM6_CR1_OPM One-pulse mode : TIM6_CR1_URS %1 2 lshift TIM6_CR1 bis! ; \ TIM6_CR1_URS Update request source : TIM6_CR1_UDIS %1 1 lshift TIM6_CR1 bis! ; \ TIM6_CR1_UDIS Update disable : TIM6_CR1_CEN %1 0 lshift TIM6_CR1 bis! ; \ TIM6_CR1_CEN Counter enable \ TIM6_CR2 (read-write) : TIM6_CR2_MMS ( %XXX -- ) 4 lshift TIM6_CR2 bis! ; \ TIM6_CR2_MMS Master mode selection \ TIM6_DIER (read-write) : TIM6_DIER_UDE %1 8 lshift TIM6_DIER bis! ; \ TIM6_DIER_UDE Update DMA request enable : TIM6_DIER_UIE %1 0 lshift TIM6_DIER bis! ; \ TIM6_DIER_UIE Update interrupt enable \ TIM6_SR (read-write) : TIM6_SR_UIF %1 0 lshift TIM6_SR bis! ; \ TIM6_SR_UIF Update interrupt flag \ TIM6_EGR (write-only) : TIM6_EGR_UG %1 0 lshift TIM6_EGR bis! ; \ TIM6_EGR_UG Update generation \ TIM6_CNT (read-write) : TIM6_CNT_CNT ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIM6_CNT bis! ; \ TIM6_CNT_CNT Low counter value \ TIM6_PSC (read-write) : TIM6_PSC_PSC ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIM6_PSC bis! ; \ TIM6_PSC_PSC Prescaler value \ TIM6_ARR (read-write) : TIM6_ARR_ARR ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIM6_ARR bis! ; \ TIM6_ARR_ARR Low Auto-reload value \ EXTI_IMR (read-write) : EXTI_IMR_MR0 %1 0 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR0 Interrupt Mask on line 0 : EXTI_IMR_MR1 %1 1 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR1 Interrupt Mask on line 1 : EXTI_IMR_MR2 %1 2 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR2 Interrupt Mask on line 2 : EXTI_IMR_MR3 %1 3 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR3 Interrupt Mask on line 3 : EXTI_IMR_MR4 %1 4 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR4 Interrupt Mask on line 4 : EXTI_IMR_MR5 %1 5 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR5 Interrupt Mask on line 5 : EXTI_IMR_MR6 %1 6 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR6 Interrupt Mask on line 6 : EXTI_IMR_MR7 %1 7 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR7 Interrupt Mask on line 7 : EXTI_IMR_MR8 %1 8 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR8 Interrupt Mask on line 8 : EXTI_IMR_MR9 %1 9 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR9 Interrupt Mask on line 9 : EXTI_IMR_MR10 %1 10 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR10 Interrupt Mask on line 10 : EXTI_IMR_MR11 %1 11 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR11 Interrupt Mask on line 11 : EXTI_IMR_MR12 %1 12 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR12 Interrupt Mask on line 12 : EXTI_IMR_MR13 %1 13 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR13 Interrupt Mask on line 13 : EXTI_IMR_MR14 %1 14 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR14 Interrupt Mask on line 14 : EXTI_IMR_MR15 %1 15 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR15 Interrupt Mask on line 15 : EXTI_IMR_MR16 %1 16 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR16 Interrupt Mask on line 16 : EXTI_IMR_MR17 %1 17 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR17 Interrupt Mask on line 17 : EXTI_IMR_MR18 %1 18 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR18 Interrupt Mask on line 18 : EXTI_IMR_MR19 %1 19 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR19 Interrupt Mask on line 19 : EXTI_IMR_MR20 %1 20 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR20 Interrupt Mask on line 20 : EXTI_IMR_MR21 %1 21 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR21 Interrupt Mask on line 21 : EXTI_IMR_MR22 %1 22 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR22 Interrupt Mask on line 22 : EXTI_IMR_MR23 %1 23 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR23 Interrupt Mask on line 23 : EXTI_IMR_MR24 %1 24 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR24 Interrupt Mask on line 24 : EXTI_IMR_MR25 %1 25 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR25 Interrupt Mask on line 25 : EXTI_IMR_MR26 %1 26 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR26 Interrupt Mask on line 26 : EXTI_IMR_MR27 %1 27 lshift EXTI_IMR bis! ; \ EXTI_IMR_MR27 Interrupt Mask on line 27 \ EXTI_EMR (read-write) : EXTI_EMR_MR0 %1 0 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR0 Event Mask on line 0 : EXTI_EMR_MR1 %1 1 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR1 Event Mask on line 1 : EXTI_EMR_MR2 %1 2 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR2 Event Mask on line 2 : EXTI_EMR_MR3 %1 3 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR3 Event Mask on line 3 : EXTI_EMR_MR4 %1 4 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR4 Event Mask on line 4 : EXTI_EMR_MR5 %1 5 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR5 Event Mask on line 5 : EXTI_EMR_MR6 %1 6 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR6 Event Mask on line 6 : EXTI_EMR_MR7 %1 7 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR7 Event Mask on line 7 : EXTI_EMR_MR8 %1 8 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR8 Event Mask on line 8 : EXTI_EMR_MR9 %1 9 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR9 Event Mask on line 9 : EXTI_EMR_MR10 %1 10 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR10 Event Mask on line 10 : EXTI_EMR_MR11 %1 11 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR11 Event Mask on line 11 : EXTI_EMR_MR12 %1 12 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR12 Event Mask on line 12 : EXTI_EMR_MR13 %1 13 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR13 Event Mask on line 13 : EXTI_EMR_MR14 %1 14 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR14 Event Mask on line 14 : EXTI_EMR_MR15 %1 15 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR15 Event Mask on line 15 : EXTI_EMR_MR16 %1 16 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR16 Event Mask on line 16 : EXTI_EMR_MR17 %1 17 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR17 Event Mask on line 17 : EXTI_EMR_MR18 %1 18 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR18 Event Mask on line 18 : EXTI_EMR_MR19 %1 19 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR19 Event Mask on line 19 : EXTI_EMR_MR20 %1 20 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR20 Event Mask on line 20 : EXTI_EMR_MR21 %1 21 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR21 Event Mask on line 21 : EXTI_EMR_MR22 %1 22 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR22 Event Mask on line 22 : EXTI_EMR_MR23 %1 23 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR23 Event Mask on line 23 : EXTI_EMR_MR24 %1 24 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR24 Event Mask on line 24 : EXTI_EMR_MR25 %1 25 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR25 Event Mask on line 25 : EXTI_EMR_MR26 %1 26 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR26 Event Mask on line 26 : EXTI_EMR_MR27 %1 27 lshift EXTI_EMR bis! ; \ EXTI_EMR_MR27 Event Mask on line 27 \ EXTI_RTSR (read-write) : EXTI_RTSR_TR0 %1 0 lshift EXTI_RTSR bis! ; \ EXTI_RTSR_TR0 Rising trigger event configuration of line 0 : EXTI_RTSR_TR1 %1 1 lshift EXTI_RTSR bis! ; \ EXTI_RTSR_TR1 Rising trigger event configuration of line 1 : EXTI_RTSR_TR2 %1 2 lshift EXTI_RTSR bis! ; \ EXTI_RTSR_TR2 Rising trigger event configuration of line 2 : EXTI_RTSR_TR3 %1 3 lshift EXTI_RTSR bis! ; \ EXTI_RTSR_TR3 Rising trigger event configuration of line 3 : EXTI_RTSR_TR4 %1 4 lshift EXTI_RTSR bis! ; \ EXTI_RTSR_TR4 Rising trigger event configuration of line 4 : EXTI_RTSR_TR5 %1 5 lshift EXTI_RTSR bis! ; \ EXTI_RTSR_TR5 Rising trigger event configuration of line 5 : EXTI_RTSR_TR6 %1 6 lshift EXTI_RTSR bis! ; \ EXTI_RTSR_TR6 Rising trigger event configuration of line 6 : EXTI_RTSR_TR7 %1 7 lshift EXTI_RTSR bis! ; \ EXTI_RTSR_TR7 Rising trigger event configuration of line 7 : EXTI_RTSR_TR8 %1 8 lshift EXTI_RTSR bis! ; \ EXTI_RTSR_TR8 Rising trigger event configuration of line 8 : EXTI_RTSR_TR9 %1 9 lshift EXTI_RTSR bis! ; \ EXTI_RTSR_TR9 Rising trigger event configuration of line 9 : EXTI_RTSR_TR10 %1 10 lshift EXTI_RTSR bis! ; \ EXTI_RTSR_TR10 Rising trigger event configuration of line 10 : EXTI_RTSR_TR11 %1 11 lshift EXTI_RTSR bis! ; \ EXTI_RTSR_TR11 Rising trigger event configuration of line 11 : EXTI_RTSR_TR12 %1 12 lshift EXTI_RTSR bis! ; \ EXTI_RTSR_TR12 Rising trigger event configuration of line 12 : EXTI_RTSR_TR13 %1 13 lshift EXTI_RTSR bis! ; \ EXTI_RTSR_TR13 Rising trigger event configuration of line 13 : EXTI_RTSR_TR14 %1 14 lshift EXTI_RTSR bis! ; \ EXTI_RTSR_TR14 Rising trigger event configuration of line 14 : EXTI_RTSR_TR15 %1 15 lshift EXTI_RTSR bis! ; \ EXTI_RTSR_TR15 Rising trigger event configuration of line 15 : EXTI_RTSR_TR16 %1 16 lshift EXTI_RTSR bis! ; \ EXTI_RTSR_TR16 Rising trigger event configuration of line 16 : EXTI_RTSR_TR17 %1 17 lshift EXTI_RTSR bis! ; \ EXTI_RTSR_TR17 Rising trigger event configuration of line 17 : EXTI_RTSR_TR19 %1 19 lshift EXTI_RTSR bis! ; \ EXTI_RTSR_TR19 Rising trigger event configuration of line 19 \ EXTI_FTSR (read-write) : EXTI_FTSR_TR0 %1 0 lshift EXTI_FTSR bis! ; \ EXTI_FTSR_TR0 Falling trigger event configuration of line 0 : EXTI_FTSR_TR1 %1 1 lshift EXTI_FTSR bis! ; \ EXTI_FTSR_TR1 Falling trigger event configuration of line 1 : EXTI_FTSR_TR2 %1 2 lshift EXTI_FTSR bis! ; \ EXTI_FTSR_TR2 Falling trigger event configuration of line 2 : EXTI_FTSR_TR3 %1 3 lshift EXTI_FTSR bis! ; \ EXTI_FTSR_TR3 Falling trigger event configuration of line 3 : EXTI_FTSR_TR4 %1 4 lshift EXTI_FTSR bis! ; \ EXTI_FTSR_TR4 Falling trigger event configuration of line 4 : EXTI_FTSR_TR5 %1 5 lshift EXTI_FTSR bis! ; \ EXTI_FTSR_TR5 Falling trigger event configuration of line 5 : EXTI_FTSR_TR6 %1 6 lshift EXTI_FTSR bis! ; \ EXTI_FTSR_TR6 Falling trigger event configuration of line 6 : EXTI_FTSR_TR7 %1 7 lshift EXTI_FTSR bis! ; \ EXTI_FTSR_TR7 Falling trigger event configuration of line 7 : EXTI_FTSR_TR8 %1 8 lshift EXTI_FTSR bis! ; \ EXTI_FTSR_TR8 Falling trigger event configuration of line 8 : EXTI_FTSR_TR9 %1 9 lshift EXTI_FTSR bis! ; \ EXTI_FTSR_TR9 Falling trigger event configuration of line 9 : EXTI_FTSR_TR10 %1 10 lshift EXTI_FTSR bis! ; \ EXTI_FTSR_TR10 Falling trigger event configuration of line 10 : EXTI_FTSR_TR11 %1 11 lshift EXTI_FTSR bis! ; \ EXTI_FTSR_TR11 Falling trigger event configuration of line 11 : EXTI_FTSR_TR12 %1 12 lshift EXTI_FTSR bis! ; \ EXTI_FTSR_TR12 Falling trigger event configuration of line 12 : EXTI_FTSR_TR13 %1 13 lshift EXTI_FTSR bis! ; \ EXTI_FTSR_TR13 Falling trigger event configuration of line 13 : EXTI_FTSR_TR14 %1 14 lshift EXTI_FTSR bis! ; \ EXTI_FTSR_TR14 Falling trigger event configuration of line 14 : EXTI_FTSR_TR15 %1 15 lshift EXTI_FTSR bis! ; \ EXTI_FTSR_TR15 Falling trigger event configuration of line 15 : EXTI_FTSR_TR16 %1 16 lshift EXTI_FTSR bis! ; \ EXTI_FTSR_TR16 Falling trigger event configuration of line 16 : EXTI_FTSR_TR17 %1 17 lshift EXTI_FTSR bis! ; \ EXTI_FTSR_TR17 Falling trigger event configuration of line 17 : EXTI_FTSR_TR19 %1 19 lshift EXTI_FTSR bis! ; \ EXTI_FTSR_TR19 Falling trigger event configuration of line 19 \ EXTI_SWIER (read-write) : EXTI_SWIER_SWIER0 %1 0 lshift EXTI_SWIER bis! ; \ EXTI_SWIER_SWIER0 Software Interrupt on line 0 : EXTI_SWIER_SWIER1 %1 1 lshift EXTI_SWIER bis! ; \ EXTI_SWIER_SWIER1 Software Interrupt on line 1 : EXTI_SWIER_SWIER2 %1 2 lshift EXTI_SWIER bis! ; \ EXTI_SWIER_SWIER2 Software Interrupt on line 2 : EXTI_SWIER_SWIER3 %1 3 lshift EXTI_SWIER bis! ; \ EXTI_SWIER_SWIER3 Software Interrupt on line 3 : EXTI_SWIER_SWIER4 %1 4 lshift EXTI_SWIER bis! ; \ EXTI_SWIER_SWIER4 Software Interrupt on line 4 : EXTI_SWIER_SWIER5 %1 5 lshift EXTI_SWIER bis! ; \ EXTI_SWIER_SWIER5 Software Interrupt on line 5 : EXTI_SWIER_SWIER6 %1 6 lshift EXTI_SWIER bis! ; \ EXTI_SWIER_SWIER6 Software Interrupt on line 6 : EXTI_SWIER_SWIER7 %1 7 lshift EXTI_SWIER bis! ; \ EXTI_SWIER_SWIER7 Software Interrupt on line 7 : EXTI_SWIER_SWIER8 %1 8 lshift EXTI_SWIER bis! ; \ EXTI_SWIER_SWIER8 Software Interrupt on line 8 : EXTI_SWIER_SWIER9 %1 9 lshift EXTI_SWIER bis! ; \ EXTI_SWIER_SWIER9 Software Interrupt on line 9 : EXTI_SWIER_SWIER10 %1 10 lshift EXTI_SWIER bis! ; \ EXTI_SWIER_SWIER10 Software Interrupt on line 10 : EXTI_SWIER_SWIER11 %1 11 lshift EXTI_SWIER bis! ; \ EXTI_SWIER_SWIER11 Software Interrupt on line 11 : EXTI_SWIER_SWIER12 %1 12 lshift EXTI_SWIER bis! ; \ EXTI_SWIER_SWIER12 Software Interrupt on line 12 : EXTI_SWIER_SWIER13 %1 13 lshift EXTI_SWIER bis! ; \ EXTI_SWIER_SWIER13 Software Interrupt on line 13 : EXTI_SWIER_SWIER14 %1 14 lshift EXTI_SWIER bis! ; \ EXTI_SWIER_SWIER14 Software Interrupt on line 14 : EXTI_SWIER_SWIER15 %1 15 lshift EXTI_SWIER bis! ; \ EXTI_SWIER_SWIER15 Software Interrupt on line 15 : EXTI_SWIER_SWIER16 %1 16 lshift EXTI_SWIER bis! ; \ EXTI_SWIER_SWIER16 Software Interrupt on line 16 : EXTI_SWIER_SWIER17 %1 17 lshift EXTI_SWIER bis! ; \ EXTI_SWIER_SWIER17 Software Interrupt on line 17 : EXTI_SWIER_SWIER19 %1 19 lshift EXTI_SWIER bis! ; \ EXTI_SWIER_SWIER19 Software Interrupt on line 19 \ EXTI_PR (read-write) : EXTI_PR_PR0 %1 0 lshift EXTI_PR bis! ; \ EXTI_PR_PR0 Pending bit 0 : EXTI_PR_PR1 %1 1 lshift EXTI_PR bis! ; \ EXTI_PR_PR1 Pending bit 1 : EXTI_PR_PR2 %1 2 lshift EXTI_PR bis! ; \ EXTI_PR_PR2 Pending bit 2 : EXTI_PR_PR3 %1 3 lshift EXTI_PR bis! ; \ EXTI_PR_PR3 Pending bit 3 : EXTI_PR_PR4 %1 4 lshift EXTI_PR bis! ; \ EXTI_PR_PR4 Pending bit 4 : EXTI_PR_PR5 %1 5 lshift EXTI_PR bis! ; \ EXTI_PR_PR5 Pending bit 5 : EXTI_PR_PR6 %1 6 lshift EXTI_PR bis! ; \ EXTI_PR_PR6 Pending bit 6 : EXTI_PR_PR7 %1 7 lshift EXTI_PR bis! ; \ EXTI_PR_PR7 Pending bit 7 : EXTI_PR_PR8 %1 8 lshift EXTI_PR bis! ; \ EXTI_PR_PR8 Pending bit 8 : EXTI_PR_PR9 %1 9 lshift EXTI_PR bis! ; \ EXTI_PR_PR9 Pending bit 9 : EXTI_PR_PR10 %1 10 lshift EXTI_PR bis! ; \ EXTI_PR_PR10 Pending bit 10 : EXTI_PR_PR11 %1 11 lshift EXTI_PR bis! ; \ EXTI_PR_PR11 Pending bit 11 : EXTI_PR_PR12 %1 12 lshift EXTI_PR bis! ; \ EXTI_PR_PR12 Pending bit 12 : EXTI_PR_PR13 %1 13 lshift EXTI_PR bis! ; \ EXTI_PR_PR13 Pending bit 13 : EXTI_PR_PR14 %1 14 lshift EXTI_PR bis! ; \ EXTI_PR_PR14 Pending bit 14 : EXTI_PR_PR15 %1 15 lshift EXTI_PR bis! ; \ EXTI_PR_PR15 Pending bit 15 : EXTI_PR_PR16 %1 16 lshift EXTI_PR bis! ; \ EXTI_PR_PR16 Pending bit 16 : EXTI_PR_PR17 %1 17 lshift EXTI_PR bis! ; \ EXTI_PR_PR17 Pending bit 17 : EXTI_PR_PR19 %1 19 lshift EXTI_PR bis! ; \ EXTI_PR_PR19 Pending bit 19 \ NVIC_ISER (read-write) : NVIC_ISER_SETENA ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift NVIC_ISER bis! ; \ NVIC_ISER_SETENA SETENA \ NVIC_ICER (read-write) : NVIC_ICER_CLRENA ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift NVIC_ICER bis! ; \ NVIC_ICER_CLRENA CLRENA \ NVIC_ISPR (read-write) : NVIC_ISPR_SETPEND ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift NVIC_ISPR bis! ; \ NVIC_ISPR_SETPEND SETPEND \ NVIC_ICPR (read-write) : NVIC_ICPR_CLRPEND ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift NVIC_ICPR bis! ; \ NVIC_ICPR_CLRPEND CLRPEND \ NVIC_IPR0 (read-write) : NVIC_IPR0_PRI_00 ( %XX -- ) 6 lshift NVIC_IPR0 bis! ; \ NVIC_IPR0_PRI_00 PRI_00 : NVIC_IPR0_PRI_01 ( %XX -- ) 14 lshift NVIC_IPR0 bis! ; \ NVIC_IPR0_PRI_01 PRI_01 : NVIC_IPR0_PRI_02 ( %XX -- ) 22 lshift NVIC_IPR0 bis! ; \ NVIC_IPR0_PRI_02 PRI_02 : NVIC_IPR0_PRI_03 ( %XX -- ) 30 lshift NVIC_IPR0 bis! ; \ NVIC_IPR0_PRI_03 PRI_03 \ NVIC_IPR1 (read-write) : NVIC_IPR1_PRI_40 ( %XX -- ) 6 lshift NVIC_IPR1 bis! ; \ NVIC_IPR1_PRI_40 PRI_40 : NVIC_IPR1_PRI_41 ( %XX -- ) 14 lshift NVIC_IPR1 bis! ; \ NVIC_IPR1_PRI_41 PRI_41 : NVIC_IPR1_PRI_42 ( %XX -- ) 22 lshift NVIC_IPR1 bis! ; \ NVIC_IPR1_PRI_42 PRI_42 : NVIC_IPR1_PRI_43 ( %XX -- ) 30 lshift NVIC_IPR1 bis! ; \ NVIC_IPR1_PRI_43 PRI_43 \ NVIC_IPR2 (read-write) : NVIC_IPR2_PRI_80 ( %XX -- ) 6 lshift NVIC_IPR2 bis! ; \ NVIC_IPR2_PRI_80 PRI_80 : NVIC_IPR2_PRI_81 ( %XX -- ) 14 lshift NVIC_IPR2 bis! ; \ NVIC_IPR2_PRI_81 PRI_81 : NVIC_IPR2_PRI_82 ( %XX -- ) 22 lshift NVIC_IPR2 bis! ; \ NVIC_IPR2_PRI_82 PRI_82 : NVIC_IPR2_PRI_83 ( %XX -- ) 30 lshift NVIC_IPR2 bis! ; \ NVIC_IPR2_PRI_83 PRI_83 \ NVIC_IPR3 (read-write) : NVIC_IPR3_PRI_120 ( %XX -- ) 6 lshift NVIC_IPR3 bis! ; \ NVIC_IPR3_PRI_120 PRI_120 : NVIC_IPR3_PRI_121 ( %XX -- ) 14 lshift NVIC_IPR3 bis! ; \ NVIC_IPR3_PRI_121 PRI_121 : NVIC_IPR3_PRI_122 ( %XX -- ) 22 lshift NVIC_IPR3 bis! ; \ NVIC_IPR3_PRI_122 PRI_122 : NVIC_IPR3_PRI_123 ( %XX -- ) 30 lshift NVIC_IPR3 bis! ; \ NVIC_IPR3_PRI_123 PRI_123 \ NVIC_IPR4 (read-write) : NVIC_IPR4_PRI_160 ( %XX -- ) 6 lshift NVIC_IPR4 bis! ; \ NVIC_IPR4_PRI_160 PRI_160 : NVIC_IPR4_PRI_161 ( %XX -- ) 14 lshift NVIC_IPR4 bis! ; \ NVIC_IPR4_PRI_161 PRI_161 : NVIC_IPR4_PRI_162 ( %XX -- ) 22 lshift NVIC_IPR4 bis! ; \ NVIC_IPR4_PRI_162 PRI_162 : NVIC_IPR4_PRI_163 ( %XX -- ) 30 lshift NVIC_IPR4 bis! ; \ NVIC_IPR4_PRI_163 PRI_163 \ NVIC_IPR5 (read-write) : NVIC_IPR5_PRI_200 ( %XX -- ) 6 lshift NVIC_IPR5 bis! ; \ NVIC_IPR5_PRI_200 PRI_200 : NVIC_IPR5_PRI_201 ( %XX -- ) 14 lshift NVIC_IPR5 bis! ; \ NVIC_IPR5_PRI_201 PRI_201 : NVIC_IPR5_PRI_202 ( %XX -- ) 22 lshift NVIC_IPR5 bis! ; \ NVIC_IPR5_PRI_202 PRI_202 : NVIC_IPR5_PRI_203 ( %XX -- ) 30 lshift NVIC_IPR5 bis! ; \ NVIC_IPR5_PRI_203 PRI_203 \ NVIC_IPR6 (read-write) : NVIC_IPR6_PRI_240 ( %XX -- ) 6 lshift NVIC_IPR6 bis! ; \ NVIC_IPR6_PRI_240 PRI_240 : NVIC_IPR6_PRI_241 ( %XX -- ) 14 lshift NVIC_IPR6 bis! ; \ NVIC_IPR6_PRI_241 PRI_241 : NVIC_IPR6_PRI_242 ( %XX -- ) 22 lshift NVIC_IPR6 bis! ; \ NVIC_IPR6_PRI_242 PRI_242 : NVIC_IPR6_PRI_243 ( %XX -- ) 30 lshift NVIC_IPR6 bis! ; \ NVIC_IPR6_PRI_243 PRI_243 \ NVIC_IPR7 (read-write) : NVIC_IPR7_PRI_280 ( %XX -- ) 6 lshift NVIC_IPR7 bis! ; \ NVIC_IPR7_PRI_280 PRI_280 : NVIC_IPR7_PRI_281 ( %XX -- ) 14 lshift NVIC_IPR7 bis! ; \ NVIC_IPR7_PRI_281 PRI_281 : NVIC_IPR7_PRI_282 ( %XX -- ) 22 lshift NVIC_IPR7 bis! ; \ NVIC_IPR7_PRI_282 PRI_282 : NVIC_IPR7_PRI_283 ( %XX -- ) 30 lshift NVIC_IPR7 bis! ; \ NVIC_IPR7_PRI_283 PRI_283 \ RCC_CR () : RCC_CR_HSION %1 0 lshift RCC_CR bis! ; \ RCC_CR_HSION Internal High Speed clock enable : RCC_CR_HSIRDY %1 1 lshift RCC_CR bis! ; \ RCC_CR_HSIRDY Internal High Speed clock ready flag : RCC_CR_HSITRIM ( %XXXXX -- ) 3 lshift RCC_CR bis! ; \ RCC_CR_HSITRIM Internal High Speed clock trimming : RCC_CR_HSICAL ( %XXXXXXXX -- ) 8 lshift RCC_CR bis! ; \ RCC_CR_HSICAL Internal High Speed clock Calibration : RCC_CR_HSEON %1 16 lshift RCC_CR bis! ; \ RCC_CR_HSEON External High Speed clock enable : RCC_CR_HSERDY %1 17 lshift RCC_CR bis! ; \ RCC_CR_HSERDY External High Speed clock ready flag : RCC_CR_HSEBYP %1 18 lshift RCC_CR bis! ; \ RCC_CR_HSEBYP External High Speed clock Bypass : RCC_CR_CSSON %1 19 lshift RCC_CR bis! ; \ RCC_CR_CSSON Clock Security System enable : RCC_CR_PLLON %1 24 lshift RCC_CR bis! ; \ RCC_CR_PLLON PLL enable : RCC_CR_PLLRDY %1 25 lshift RCC_CR bis! ; \ RCC_CR_PLLRDY PLL clock ready flag \ RCC_CFGR () : RCC_CFGR_SW ( %XX -- ) 0 lshift RCC_CFGR bis! ; \ RCC_CFGR_SW System clock Switch : RCC_CFGR_SWS ( %XX -- ) 2 lshift RCC_CFGR bis! ; \ RCC_CFGR_SWS System Clock Switch Status : RCC_CFGR_HPRE ( %XXXX -- ) 4 lshift RCC_CFGR bis! ; \ RCC_CFGR_HPRE AHB prescaler : RCC_CFGR_PPRE ( %XXX -- ) 8 lshift RCC_CFGR bis! ; \ RCC_CFGR_PPRE APB Low speed prescaler APB1 : RCC_CFGR_ADCPRE ( %XX -- ) 14 lshift RCC_CFGR bis! ; \ RCC_CFGR_ADCPRE ADC prescaler : RCC_CFGR_PLLSRC ( %XX -- ) 15 lshift RCC_CFGR bis! ; \ RCC_CFGR_PLLSRC PLL entry clock source : RCC_CFGR_PLLXTPRE %1 17 lshift RCC_CFGR bis! ; \ RCC_CFGR_PLLXTPRE HSE divider for PLL entry : RCC_CFGR_PLLMUL ( %XXXX -- ) 18 lshift RCC_CFGR bis! ; \ RCC_CFGR_PLLMUL PLL Multiplication Factor : RCC_CFGR_MCO ( %XXX -- ) 24 lshift RCC_CFGR bis! ; \ RCC_CFGR_MCO Microcontroller clock output \ RCC_CIR () : RCC_CIR_LSIRDYF %1 0 lshift RCC_CIR bis! ; \ RCC_CIR_LSIRDYF LSI Ready Interrupt flag : RCC_CIR_LSERDYF %1 1 lshift RCC_CIR bis! ; \ RCC_CIR_LSERDYF LSE Ready Interrupt flag : RCC_CIR_HSIRDYF %1 2 lshift RCC_CIR bis! ; \ RCC_CIR_HSIRDYF HSI Ready Interrupt flag : RCC_CIR_HSERDYF %1 3 lshift RCC_CIR bis! ; \ RCC_CIR_HSERDYF HSE Ready Interrupt flag : RCC_CIR_PLLRDYF %1 4 lshift RCC_CIR bis! ; \ RCC_CIR_PLLRDYF PLL Ready Interrupt flag : RCC_CIR_HSI14RDYF %1 5 lshift RCC_CIR bis! ; \ RCC_CIR_HSI14RDYF HSI14 ready interrupt flag : RCC_CIR_CSSF %1 7 lshift RCC_CIR bis! ; \ RCC_CIR_CSSF Clock Security System Interrupt flag : RCC_CIR_LSIRDYIE %1 8 lshift RCC_CIR bis! ; \ RCC_CIR_LSIRDYIE LSI Ready Interrupt Enable : RCC_CIR_LSERDYIE %1 9 lshift RCC_CIR bis! ; \ RCC_CIR_LSERDYIE LSE Ready Interrupt Enable : RCC_CIR_HSIRDYIE %1 10 lshift RCC_CIR bis! ; \ RCC_CIR_HSIRDYIE HSI Ready Interrupt Enable : RCC_CIR_HSERDYIE %1 11 lshift RCC_CIR bis! ; \ RCC_CIR_HSERDYIE HSE Ready Interrupt Enable : RCC_CIR_PLLRDYIE %1 12 lshift RCC_CIR bis! ; \ RCC_CIR_PLLRDYIE PLL Ready Interrupt Enable : RCC_CIR_HSI14RDYE %1 13 lshift RCC_CIR bis! ; \ RCC_CIR_HSI14RDYE HSI14 ready interrupt enable : RCC_CIR_LSIRDYC %1 16 lshift RCC_CIR bis! ; \ RCC_CIR_LSIRDYC LSI Ready Interrupt Clear : RCC_CIR_LSERDYC %1 17 lshift RCC_CIR bis! ; \ RCC_CIR_LSERDYC LSE Ready Interrupt Clear : RCC_CIR_HSIRDYC %1 18 lshift RCC_CIR bis! ; \ RCC_CIR_HSIRDYC HSI Ready Interrupt Clear : RCC_CIR_HSERDYC %1 19 lshift RCC_CIR bis! ; \ RCC_CIR_HSERDYC HSE Ready Interrupt Clear : RCC_CIR_PLLRDYC %1 20 lshift RCC_CIR bis! ; \ RCC_CIR_PLLRDYC PLL Ready Interrupt Clear : RCC_CIR_HSI14RDYC %1 21 lshift RCC_CIR bis! ; \ RCC_CIR_HSI14RDYC HSI 14 MHz Ready Interrupt Clear : RCC_CIR_CSSC %1 23 lshift RCC_CIR bis! ; \ RCC_CIR_CSSC Clock security system interrupt clear \ RCC_APB2RSTR (read-write) : RCC_APB2RSTR_SYSCFGRST %1 0 lshift RCC_APB2RSTR bis! ; \ RCC_APB2RSTR_SYSCFGRST SYSCFG and COMP reset : RCC_APB2RSTR_ADCRST %1 9 lshift RCC_APB2RSTR bis! ; \ RCC_APB2RSTR_ADCRST ADC interface reset : RCC_APB2RSTR_TIM1RST %1 11 lshift RCC_APB2RSTR bis! ; \ RCC_APB2RSTR_TIM1RST TIM1 timer reset : RCC_APB2RSTR_SPI1RST %1 12 lshift RCC_APB2RSTR bis! ; \ RCC_APB2RSTR_SPI1RST SPI 1 reset : RCC_APB2RSTR_USART1RST %1 14 lshift RCC_APB2RSTR bis! ; \ RCC_APB2RSTR_USART1RST USART1 reset : RCC_APB2RSTR_TIM15RST %1 16 lshift RCC_APB2RSTR bis! ; \ RCC_APB2RSTR_TIM15RST TIM15 timer reset : RCC_APB2RSTR_TIM16RST %1 17 lshift RCC_APB2RSTR bis! ; \ RCC_APB2RSTR_TIM16RST TIM16 timer reset : RCC_APB2RSTR_TIM17RST %1 18 lshift RCC_APB2RSTR bis! ; \ RCC_APB2RSTR_TIM17RST TIM17 timer reset : RCC_APB2RSTR_DBGMCURST %1 22 lshift RCC_APB2RSTR bis! ; \ RCC_APB2RSTR_DBGMCURST Debug MCU reset \ RCC_APB1RSTR (read-write) : RCC_APB1RSTR_TIM2RST %1 0 lshift RCC_APB1RSTR bis! ; \ RCC_APB1RSTR_TIM2RST Timer 2 reset : RCC_APB1RSTR_TIM3RST %1 1 lshift RCC_APB1RSTR bis! ; \ RCC_APB1RSTR_TIM3RST Timer 3 reset : RCC_APB1RSTR_TIM6RST %1 4 lshift RCC_APB1RSTR bis! ; \ RCC_APB1RSTR_TIM6RST Timer 6 reset : RCC_APB1RSTR_TIM14RST %1 8 lshift RCC_APB1RSTR bis! ; \ RCC_APB1RSTR_TIM14RST Timer 14 reset : RCC_APB1RSTR_WWDGRST %1 11 lshift RCC_APB1RSTR bis! ; \ RCC_APB1RSTR_WWDGRST Window watchdog reset : RCC_APB1RSTR_SPI2RST %1 14 lshift RCC_APB1RSTR bis! ; \ RCC_APB1RSTR_SPI2RST SPI2 reset : RCC_APB1RSTR_USART2RST %1 17 lshift RCC_APB1RSTR bis! ; \ RCC_APB1RSTR_USART2RST USART 2 reset : RCC_APB1RSTR_I2C1RST %1 21 lshift RCC_APB1RSTR bis! ; \ RCC_APB1RSTR_I2C1RST I2C1 reset : RCC_APB1RSTR_I2C2RST %1 22 lshift RCC_APB1RSTR bis! ; \ RCC_APB1RSTR_I2C2RST I2C2 reset : RCC_APB1RSTR_PWRRST %1 28 lshift RCC_APB1RSTR bis! ; \ RCC_APB1RSTR_PWRRST Power interface reset : RCC_APB1RSTR_DACRST %1 29 lshift RCC_APB1RSTR bis! ; \ RCC_APB1RSTR_DACRST DAC interface reset : RCC_APB1RSTR_CECRST %1 30 lshift RCC_APB1RSTR bis! ; \ RCC_APB1RSTR_CECRST HDMI CEC reset \ RCC_AHBENR (read-write) : RCC_AHBENR_DMAEN %1 0 lshift RCC_AHBENR bis! ; \ RCC_AHBENR_DMAEN DMA1 clock enable : RCC_AHBENR_SRAMEN %1 2 lshift RCC_AHBENR bis! ; \ RCC_AHBENR_SRAMEN SRAM interface clock enable : RCC_AHBENR_FLITFEN %1 4 lshift RCC_AHBENR bis! ; \ RCC_AHBENR_FLITFEN FLITF clock enable : RCC_AHBENR_CRCEN %1 6 lshift RCC_AHBENR bis! ; \ RCC_AHBENR_CRCEN CRC clock enable : RCC_AHBENR_IOPAEN %1 17 lshift RCC_AHBENR bis! ; \ RCC_AHBENR_IOPAEN I/O port A clock enable : RCC_AHBENR_IOPBEN %1 18 lshift RCC_AHBENR bis! ; \ RCC_AHBENR_IOPBEN I/O port B clock enable : RCC_AHBENR_IOPCEN %1 19 lshift RCC_AHBENR bis! ; \ RCC_AHBENR_IOPCEN I/O port C clock enable : RCC_AHBENR_IOPDEN %1 20 lshift RCC_AHBENR bis! ; \ RCC_AHBENR_IOPDEN I/O port D clock enable : RCC_AHBENR_IOPFEN %1 22 lshift RCC_AHBENR bis! ; \ RCC_AHBENR_IOPFEN I/O port F clock enable : RCC_AHBENR_TSCEN %1 24 lshift RCC_AHBENR bis! ; \ RCC_AHBENR_TSCEN Touch sensing controller clock enable \ RCC_APB2ENR (read-write) : RCC_APB2ENR_SYSCFGEN %1 0 lshift RCC_APB2ENR bis! ; \ RCC_APB2ENR_SYSCFGEN SYSCFG clock enable : RCC_APB2ENR_ADCEN %1 9 lshift RCC_APB2ENR bis! ; \ RCC_APB2ENR_ADCEN ADC 1 interface clock enable : RCC_APB2ENR_TIM1EN %1 11 lshift RCC_APB2ENR bis! ; \ RCC_APB2ENR_TIM1EN TIM1 Timer clock enable : RCC_APB2ENR_SPI1EN %1 12 lshift RCC_APB2ENR bis! ; \ RCC_APB2ENR_SPI1EN SPI 1 clock enable : RCC_APB2ENR_USART1EN %1 14 lshift RCC_APB2ENR bis! ; \ RCC_APB2ENR_USART1EN USART1 clock enable : RCC_APB2ENR_TIM15EN %1 16 lshift RCC_APB2ENR bis! ; \ RCC_APB2ENR_TIM15EN TIM15 timer clock enable : RCC_APB2ENR_TIM16EN %1 17 lshift RCC_APB2ENR bis! ; \ RCC_APB2ENR_TIM16EN TIM16 timer clock enable : RCC_APB2ENR_TIM17EN %1 18 lshift RCC_APB2ENR bis! ; \ RCC_APB2ENR_TIM17EN TIM17 timer clock enable : RCC_APB2ENR_DBGMCUEN %1 22 lshift RCC_APB2ENR bis! ; \ RCC_APB2ENR_DBGMCUEN MCU debug module clock enable \ RCC_APB1ENR (read-write) : RCC_APB1ENR_TIM2EN %1 0 lshift RCC_APB1ENR bis! ; \ RCC_APB1ENR_TIM2EN Timer 2 clock enable : RCC_APB1ENR_TIM3EN %1 1 lshift RCC_APB1ENR bis! ; \ RCC_APB1ENR_TIM3EN Timer 3 clock enable : RCC_APB1ENR_TIM6EN %1 4 lshift RCC_APB1ENR bis! ; \ RCC_APB1ENR_TIM6EN Timer 6 clock enable : RCC_APB1ENR_TIM14EN %1 8 lshift RCC_APB1ENR bis! ; \ RCC_APB1ENR_TIM14EN Timer 14 clock enable : RCC_APB1ENR_WWDGEN %1 11 lshift RCC_APB1ENR bis! ; \ RCC_APB1ENR_WWDGEN Window watchdog clock enable : RCC_APB1ENR_SPI2EN %1 14 lshift RCC_APB1ENR bis! ; \ RCC_APB1ENR_SPI2EN SPI 2 clock enable : RCC_APB1ENR_USART2EN %1 17 lshift RCC_APB1ENR bis! ; \ RCC_APB1ENR_USART2EN USART 2 clock enable : RCC_APB1ENR_I2C1EN %1 21 lshift RCC_APB1ENR bis! ; \ RCC_APB1ENR_I2C1EN I2C 1 clock enable : RCC_APB1ENR_I2C2EN %1 22 lshift RCC_APB1ENR bis! ; \ RCC_APB1ENR_I2C2EN I2C 2 clock enable : RCC_APB1ENR_PWREN %1 28 lshift RCC_APB1ENR bis! ; \ RCC_APB1ENR_PWREN Power interface clock enable : RCC_APB1ENR_DACEN %1 29 lshift RCC_APB1ENR bis! ; \ RCC_APB1ENR_DACEN DAC interface clock enable : RCC_APB1ENR_CECEN %1 30 lshift RCC_APB1ENR bis! ; \ RCC_APB1ENR_CECEN HDMI CEC interface clock enable \ RCC_BDCR () : RCC_BDCR_LSEON %1 0 lshift RCC_BDCR bis! ; \ RCC_BDCR_LSEON External Low Speed oscillator enable : RCC_BDCR_LSERDY %1 1 lshift RCC_BDCR bis! ; \ RCC_BDCR_LSERDY External Low Speed oscillator ready : RCC_BDCR_LSEBYP %1 2 lshift RCC_BDCR bis! ; \ RCC_BDCR_LSEBYP External Low Speed oscillator bypass : RCC_BDCR_LSEDRV ( %XX -- ) 3 lshift RCC_BDCR bis! ; \ RCC_BDCR_LSEDRV LSE oscillator drive capability : RCC_BDCR_RTCSEL ( %XX -- ) 8 lshift RCC_BDCR bis! ; \ RCC_BDCR_RTCSEL RTC clock source selection : RCC_BDCR_RTCEN %1 15 lshift RCC_BDCR bis! ; \ RCC_BDCR_RTCEN RTC clock enable : RCC_BDCR_BDRST %1 16 lshift RCC_BDCR bis! ; \ RCC_BDCR_BDRST Backup domain software reset \ RCC_CSR () : RCC_CSR_LSION %1 0 lshift RCC_CSR bis! ; \ RCC_CSR_LSION Internal low speed oscillator enable : RCC_CSR_LSIRDY %1 1 lshift RCC_CSR bis! ; \ RCC_CSR_LSIRDY Internal low speed oscillator ready : RCC_CSR_RMVF %1 24 lshift RCC_CSR bis! ; \ RCC_CSR_RMVF Remove reset flag : RCC_CSR_OBLRSTF %1 25 lshift RCC_CSR bis! ; \ RCC_CSR_OBLRSTF Option byte loader reset flag : RCC_CSR_PINRSTF %1 26 lshift RCC_CSR bis! ; \ RCC_CSR_PINRSTF PIN reset flag : RCC_CSR_PORRSTF %1 27 lshift RCC_CSR bis! ; \ RCC_CSR_PORRSTF POR/PDR reset flag : RCC_CSR_SFTRSTF %1 28 lshift RCC_CSR bis! ; \ RCC_CSR_SFTRSTF Software reset flag : RCC_CSR_IWDGRSTF %1 29 lshift RCC_CSR bis! ; \ RCC_CSR_IWDGRSTF Independent watchdog reset flag : RCC_CSR_WWDGRSTF %1 30 lshift RCC_CSR bis! ; \ RCC_CSR_WWDGRSTF Window watchdog reset flag : RCC_CSR_LPWRRSTF %1 31 lshift RCC_CSR bis! ; \ RCC_CSR_LPWRRSTF Low-power reset flag \ RCC_AHBRSTR (read-write) : RCC_AHBRSTR_IOPARST %1 17 lshift RCC_AHBRSTR bis! ; \ RCC_AHBRSTR_IOPARST I/O port A reset : RCC_AHBRSTR_IOPBRST %1 18 lshift RCC_AHBRSTR bis! ; \ RCC_AHBRSTR_IOPBRST I/O port B reset : RCC_AHBRSTR_IOPCRST %1 19 lshift RCC_AHBRSTR bis! ; \ RCC_AHBRSTR_IOPCRST I/O port C reset : RCC_AHBRSTR_IOPDRST %1 20 lshift RCC_AHBRSTR bis! ; \ RCC_AHBRSTR_IOPDRST I/O port D reset : RCC_AHBRSTR_IOPFRST %1 22 lshift RCC_AHBRSTR bis! ; \ RCC_AHBRSTR_IOPFRST I/O port F reset : RCC_AHBRSTR_TSCRST %1 24 lshift RCC_AHBRSTR bis! ; \ RCC_AHBRSTR_TSCRST Touch sensing controller reset \ RCC_CFGR2 (read-write) : RCC_CFGR2_PREDIV ( %XXXX -- ) 0 lshift RCC_CFGR2 bis! ; \ RCC_CFGR2_PREDIV PREDIV division factor \ RCC_CFGR3 (read-write) : RCC_CFGR3_USART1SW ( %XX -- ) 0 lshift RCC_CFGR3 bis! ; \ RCC_CFGR3_USART1SW USART1 clock source selection : RCC_CFGR3_I2C1SW %1 4 lshift RCC_CFGR3 bis! ; \ RCC_CFGR3_I2C1SW I2C1 clock source selection : RCC_CFGR3_CECSW %1 6 lshift RCC_CFGR3 bis! ; \ RCC_CFGR3_CECSW HDMI CEC clock source selection : RCC_CFGR3_ADCSW %1 8 lshift RCC_CFGR3 bis! ; \ RCC_CFGR3_ADCSW ADC clock source selection \ RCC_CR2 () : RCC_CR2_HSI14ON %1 0 lshift RCC_CR2 bis! ; \ RCC_CR2_HSI14ON HSI14 clock enable : RCC_CR2_HSI14RDY %1 1 lshift RCC_CR2 bis! ; \ RCC_CR2_HSI14RDY HR14 clock ready flag : RCC_CR2_HSI14DIS %1 2 lshift RCC_CR2 bis! ; \ RCC_CR2_HSI14DIS HSI14 clock request from ADC disable : RCC_CR2_HSI14TRIM ( %XXXXX -- ) 3 lshift RCC_CR2 bis! ; \ RCC_CR2_HSI14TRIM HSI14 clock trimming : RCC_CR2_HSI14CAL ( %XXXXXXXX -- ) 8 lshift RCC_CR2 bis! ; \ RCC_CR2_HSI14CAL HSI14 clock calibration \ SYSCFG_CFGR1 (read-write) : SYSCFG_CFGR1_I2C_PB9_FM %1 19 lshift SYSCFG_CFGR1 bis! ; \ SYSCFG_CFGR1_I2C_PB9_FM Fast Mode Plus FM+ driving capability activation bits. : SYSCFG_CFGR1_I2C_PB8_FM %1 18 lshift SYSCFG_CFGR1 bis! ; \ SYSCFG_CFGR1_I2C_PB8_FM Fast Mode Plus FM+ driving capability activation bits. : SYSCFG_CFGR1_I2C_PB7_FM %1 17 lshift SYSCFG_CFGR1 bis! ; \ SYSCFG_CFGR1_I2C_PB7_FM Fast Mode Plus FM+ driving capability activation bits. : SYSCFG_CFGR1_I2C_PB6_FM %1 16 lshift SYSCFG_CFGR1 bis! ; \ SYSCFG_CFGR1_I2C_PB6_FM Fast Mode Plus FM+ driving capability activation bits. : SYSCFG_CFGR1_TIM17_DMA_RMP %1 12 lshift SYSCFG_CFGR1 bis! ; \ SYSCFG_CFGR1_TIM17_DMA_RMP TIM17 DMA request remapping bit : SYSCFG_CFGR1_TIM16_DMA_RMP %1 11 lshift SYSCFG_CFGR1 bis! ; \ SYSCFG_CFGR1_TIM16_DMA_RMP TIM16 DMA request remapping bit : SYSCFG_CFGR1_USART1_RX_DMA_RMP %1 10 lshift SYSCFG_CFGR1 bis! ; \ SYSCFG_CFGR1_USART1_RX_DMA_RMP USART1_RX DMA request remapping bit : SYSCFG_CFGR1_USART1_TX_DMA_RMP %1 9 lshift SYSCFG_CFGR1 bis! ; \ SYSCFG_CFGR1_USART1_TX_DMA_RMP USART1_TX DMA remapping bit : SYSCFG_CFGR1_ADC_DMA_RMP %1 8 lshift SYSCFG_CFGR1 bis! ; \ SYSCFG_CFGR1_ADC_DMA_RMP ADC DMA remapping bit : SYSCFG_CFGR1_MEM_MODE ( %XX -- ) 0 lshift SYSCFG_CFGR1 bis! ; \ SYSCFG_CFGR1_MEM_MODE Memory mapping selection bits \ SYSCFG_EXTICR1 (read-write) : SYSCFG_EXTICR1_EXTI3 ( %XXXX -- ) 12 lshift SYSCFG_EXTICR1 bis! ; \ SYSCFG_EXTICR1_EXTI3 EXTI 3 configuration bits : SYSCFG_EXTICR1_EXTI2 ( %XXXX -- ) 8 lshift SYSCFG_EXTICR1 bis! ; \ SYSCFG_EXTICR1_EXTI2 EXTI 2 configuration bits : SYSCFG_EXTICR1_EXTI1 ( %XXXX -- ) 4 lshift SYSCFG_EXTICR1 bis! ; \ SYSCFG_EXTICR1_EXTI1 EXTI 1 configuration bits : SYSCFG_EXTICR1_EXTI0 ( %XXXX -- ) 0 lshift SYSCFG_EXTICR1 bis! ; \ SYSCFG_EXTICR1_EXTI0 EXTI 0 configuration bits \ SYSCFG_EXTICR2 (read-write) : SYSCFG_EXTICR2_EXTI7 ( %XXXX -- ) 12 lshift SYSCFG_EXTICR2 bis! ; \ SYSCFG_EXTICR2_EXTI7 EXTI 7 configuration bits : SYSCFG_EXTICR2_EXTI6 ( %XXXX -- ) 8 lshift SYSCFG_EXTICR2 bis! ; \ SYSCFG_EXTICR2_EXTI6 EXTI 6 configuration bits : SYSCFG_EXTICR2_EXTI5 ( %XXXX -- ) 4 lshift SYSCFG_EXTICR2 bis! ; \ SYSCFG_EXTICR2_EXTI5 EXTI 5 configuration bits : SYSCFG_EXTICR2_EXTI4 ( %XXXX -- ) 0 lshift SYSCFG_EXTICR2 bis! ; \ SYSCFG_EXTICR2_EXTI4 EXTI 4 configuration bits \ SYSCFG_EXTICR3 (read-write) : SYSCFG_EXTICR3_EXTI11 ( %XXXX -- ) 12 lshift SYSCFG_EXTICR3 bis! ; \ SYSCFG_EXTICR3_EXTI11 EXTI 11 configuration bits : SYSCFG_EXTICR3_EXTI10 ( %XXXX -- ) 8 lshift SYSCFG_EXTICR3 bis! ; \ SYSCFG_EXTICR3_EXTI10 EXTI 10 configuration bits : SYSCFG_EXTICR3_EXTI9 ( %XXXX -- ) 4 lshift SYSCFG_EXTICR3 bis! ; \ SYSCFG_EXTICR3_EXTI9 EXTI 9 configuration bits : SYSCFG_EXTICR3_EXTI8 ( %XXXX -- ) 0 lshift SYSCFG_EXTICR3 bis! ; \ SYSCFG_EXTICR3_EXTI8 EXTI 8 configuration bits \ SYSCFG_EXTICR4 (read-write) : SYSCFG_EXTICR4_EXTI15 ( %XXXX -- ) 12 lshift SYSCFG_EXTICR4 bis! ; \ SYSCFG_EXTICR4_EXTI15 EXTI 15 configuration bits : SYSCFG_EXTICR4_EXTI14 ( %XXXX -- ) 8 lshift SYSCFG_EXTICR4 bis! ; \ SYSCFG_EXTICR4_EXTI14 EXTI 14 configuration bits : SYSCFG_EXTICR4_EXTI13 ( %XXXX -- ) 4 lshift SYSCFG_EXTICR4 bis! ; \ SYSCFG_EXTICR4_EXTI13 EXTI 13 configuration bits : SYSCFG_EXTICR4_EXTI12 ( %XXXX -- ) 0 lshift SYSCFG_EXTICR4 bis! ; \ SYSCFG_EXTICR4_EXTI12 EXTI 12 configuration bits \ SYSCFG_CFGR2 (read-write) : SYSCFG_CFGR2_SRAM_PEF %1 8 lshift SYSCFG_CFGR2 bis! ; \ SYSCFG_CFGR2_SRAM_PEF SRAM parity flag : SYSCFG_CFGR2_PVD_LOCK %1 2 lshift SYSCFG_CFGR2 bis! ; \ SYSCFG_CFGR2_PVD_LOCK PVD lock enable bit : SYSCFG_CFGR2_SRAM_PARITY_LOCK %1 1 lshift SYSCFG_CFGR2 bis! ; \ SYSCFG_CFGR2_SRAM_PARITY_LOCK SRAM parity lock bit : SYSCFG_CFGR2_LOCUP_LOCK %1 0 lshift SYSCFG_CFGR2 bis! ; \ SYSCFG_CFGR2_LOCUP_LOCK Cortex-M0 LOCKUP bit enable bit \ USART1_CR1 (read-write) : USART1_CR1_EOBIE %1 27 lshift USART1_CR1 bis! ; \ USART1_CR1_EOBIE End of Block interrupt enable : USART1_CR1_RTOIE %1 26 lshift USART1_CR1 bis! ; \ USART1_CR1_RTOIE Receiver timeout interrupt enable : USART1_CR1_DEAT ( %XXXXX -- ) 21 lshift USART1_CR1 bis! ; \ USART1_CR1_DEAT Driver Enable assertion time : USART1_CR1_DEDT ( %XXXXX -- ) 16 lshift USART1_CR1 bis! ; \ USART1_CR1_DEDT Driver Enable deassertion time : USART1_CR1_OVER8 %1 15 lshift USART1_CR1 bis! ; \ USART1_CR1_OVER8 Oversampling mode : USART1_CR1_CMIE %1 14 lshift USART1_CR1 bis! ; \ USART1_CR1_CMIE Character match interrupt enable : USART1_CR1_MME %1 13 lshift USART1_CR1 bis! ; \ USART1_CR1_MME Mute mode enable : USART1_CR1_M %1 12 lshift USART1_CR1 bis! ; \ USART1_CR1_M Word length : USART1_CR1_WAKE %1 11 lshift USART1_CR1 bis! ; \ USART1_CR1_WAKE Receiver wakeup method : USART1_CR1_PCE %1 10 lshift USART1_CR1 bis! ; \ USART1_CR1_PCE Parity control enable : USART1_CR1_PS %1 9 lshift USART1_CR1 bis! ; \ USART1_CR1_PS Parity selection : USART1_CR1_PEIE %1 8 lshift USART1_CR1 bis! ; \ USART1_CR1_PEIE PE interrupt enable : USART1_CR1_TXEIE %1 7 lshift USART1_CR1 bis! ; \ USART1_CR1_TXEIE interrupt enable : USART1_CR1_TCIE %1 6 lshift USART1_CR1 bis! ; \ USART1_CR1_TCIE Transmission complete interrupt enable : USART1_CR1_RXNEIE %1 5 lshift USART1_CR1 bis! ; \ USART1_CR1_RXNEIE RXNE interrupt enable : USART1_CR1_IDLEIE %1 4 lshift USART1_CR1 bis! ; \ USART1_CR1_IDLEIE IDLE interrupt enable : USART1_CR1_TE %1 3 lshift USART1_CR1 bis! ; \ USART1_CR1_TE Transmitter enable : USART1_CR1_RE %1 2 lshift USART1_CR1 bis! ; \ USART1_CR1_RE Receiver enable : USART1_CR1_UESM %1 1 lshift USART1_CR1 bis! ; \ USART1_CR1_UESM USART enable in Stop mode : USART1_CR1_UE %1 0 lshift USART1_CR1 bis! ; \ USART1_CR1_UE USART enable \ USART1_CR2 (read-write) : USART1_CR2_ADD4 ( %XXXX -- ) 28 lshift USART1_CR2 bis! ; \ USART1_CR2_ADD4 Address of the USART node : USART1_CR2_ADD0 ( %XXXX -- ) 24 lshift USART1_CR2 bis! ; \ USART1_CR2_ADD0 Address of the USART node : USART1_CR2_RTOEN %1 23 lshift USART1_CR2 bis! ; \ USART1_CR2_RTOEN Receiver timeout enable : USART1_CR2_ABRMOD ( %XX -- ) 21 lshift USART1_CR2 bis! ; \ USART1_CR2_ABRMOD Auto baud rate mode : USART1_CR2_ABREN %1 20 lshift USART1_CR2 bis! ; \ USART1_CR2_ABREN Auto baud rate enable : USART1_CR2_MSBFIRST %1 19 lshift USART1_CR2 bis! ; \ USART1_CR2_MSBFIRST Most significant bit first : USART1_CR2_DATAINV %1 18 lshift USART1_CR2 bis! ; \ USART1_CR2_DATAINV Binary data inversion : USART1_CR2_TXINV %1 17 lshift USART1_CR2 bis! ; \ USART1_CR2_TXINV TX pin active level inversion : USART1_CR2_RXINV %1 16 lshift USART1_CR2 bis! ; \ USART1_CR2_RXINV RX pin active level inversion : USART1_CR2_SWAP %1 15 lshift USART1_CR2 bis! ; \ USART1_CR2_SWAP Swap TX/RX pins : USART1_CR2_LINEN %1 14 lshift USART1_CR2 bis! ; \ USART1_CR2_LINEN LIN mode enable : USART1_CR2_STOP ( %XX -- ) 12 lshift USART1_CR2 bis! ; \ USART1_CR2_STOP STOP bits : USART1_CR2_CLKEN %1 11 lshift USART1_CR2 bis! ; \ USART1_CR2_CLKEN Clock enable : USART1_CR2_CPOL %1 10 lshift USART1_CR2 bis! ; \ USART1_CR2_CPOL Clock polarity : USART1_CR2_CPHA %1 9 lshift USART1_CR2 bis! ; \ USART1_CR2_CPHA Clock phase : USART1_CR2_LBCL %1 8 lshift USART1_CR2 bis! ; \ USART1_CR2_LBCL Last bit clock pulse : USART1_CR2_LBDIE %1 6 lshift USART1_CR2 bis! ; \ USART1_CR2_LBDIE LIN break detection interrupt enable : USART1_CR2_LBDL %1 5 lshift USART1_CR2 bis! ; \ USART1_CR2_LBDL LIN break detection length : USART1_CR2_ADDM7 %1 4 lshift USART1_CR2 bis! ; \ USART1_CR2_ADDM7 7-bit Address Detection/4-bit Address Detection \ USART1_CR3 (read-write) : USART1_CR3_WUFIE %1 22 lshift USART1_CR3 bis! ; \ USART1_CR3_WUFIE Wakeup from Stop mode interrupt enable : USART1_CR3_WUS ( %XX -- ) 20 lshift USART1_CR3 bis! ; \ USART1_CR3_WUS Wakeup from Stop mode interrupt flag selection : USART1_CR3_SCARCNT ( %XXX -- ) 17 lshift USART1_CR3 bis! ; \ USART1_CR3_SCARCNT Smartcard auto-retry count : USART1_CR3_DEP %1 15 lshift USART1_CR3 bis! ; \ USART1_CR3_DEP Driver enable polarity selection : USART1_CR3_DEM %1 14 lshift USART1_CR3 bis! ; \ USART1_CR3_DEM Driver enable mode : USART1_CR3_DDRE %1 13 lshift USART1_CR3 bis! ; \ USART1_CR3_DDRE DMA Disable on Reception Error : USART1_CR3_OVRDIS %1 12 lshift USART1_CR3 bis! ; \ USART1_CR3_OVRDIS Overrun Disable : USART1_CR3_ONEBIT %1 11 lshift USART1_CR3 bis! ; \ USART1_CR3_ONEBIT One sample bit method enable : USART1_CR3_CTSIE %1 10 lshift USART1_CR3 bis! ; \ USART1_CR3_CTSIE CTS interrupt enable : USART1_CR3_CTSE %1 9 lshift USART1_CR3 bis! ; \ USART1_CR3_CTSE CTS enable : USART1_CR3_RTSE %1 8 lshift USART1_CR3 bis! ; \ USART1_CR3_RTSE RTS enable : USART1_CR3_DMAT %1 7 lshift USART1_CR3 bis! ; \ USART1_CR3_DMAT DMA enable transmitter : USART1_CR3_DMAR %1 6 lshift USART1_CR3 bis! ; \ USART1_CR3_DMAR DMA enable receiver : USART1_CR3_SCEN %1 5 lshift USART1_CR3 bis! ; \ USART1_CR3_SCEN Smartcard mode enable : USART1_CR3_NACK %1 4 lshift USART1_CR3 bis! ; \ USART1_CR3_NACK Smartcard NACK enable : USART1_CR3_HDSEL %1 3 lshift USART1_CR3 bis! ; \ USART1_CR3_HDSEL Half-duplex selection : USART1_CR3_IRLP %1 2 lshift USART1_CR3 bis! ; \ USART1_CR3_IRLP IrDA low-power : USART1_CR3_IREN %1 1 lshift USART1_CR3 bis! ; \ USART1_CR3_IREN IrDA mode enable : USART1_CR3_EIE %1 0 lshift USART1_CR3 bis! ; \ USART1_CR3_EIE Error interrupt enable \ USART1_BRR (read-write) : USART1_BRR_DIV_Mantissa ( %XXXXXXXXXXX -- ) 4 lshift USART1_BRR bis! ; \ USART1_BRR_DIV_Mantissa mantissa of USARTDIV : USART1_BRR_DIV_Fraction ( %XXXX -- ) 0 lshift USART1_BRR bis! ; \ USART1_BRR_DIV_Fraction fraction of USARTDIV \ USART1_GTPR (read-write) : USART1_GTPR_GT ( %XXXXXXXX -- ) 8 lshift USART1_GTPR bis! ; \ USART1_GTPR_GT Guard time value : USART1_GTPR_PSC ( %XXXXXXXX -- ) 0 lshift USART1_GTPR bis! ; \ USART1_GTPR_PSC Prescaler value \ USART1_RTOR (read-write) : USART1_RTOR_BLEN ( %XXXXXXXX -- ) 24 lshift USART1_RTOR bis! ; \ USART1_RTOR_BLEN Block Length : USART1_RTOR_RTO ( %XXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift USART1_RTOR bis! ; \ USART1_RTOR_RTO Receiver timeout value \ USART1_RQR (read-write) : USART1_RQR_TXFRQ %1 4 lshift USART1_RQR bis! ; \ USART1_RQR_TXFRQ Transmit data flush request : USART1_RQR_RXFRQ %1 3 lshift USART1_RQR bis! ; \ USART1_RQR_RXFRQ Receive data flush request : USART1_RQR_MMRQ %1 2 lshift USART1_RQR bis! ; \ USART1_RQR_MMRQ Mute mode request : USART1_RQR_SBKRQ %1 1 lshift USART1_RQR bis! ; \ USART1_RQR_SBKRQ Send break request : USART1_RQR_ABRRQ %1 0 lshift USART1_RQR bis! ; \ USART1_RQR_ABRRQ Auto baud rate request \ USART1_ISR (read-only) : USART1_ISR_REACK %1 22 lshift USART1_ISR bis! ; \ USART1_ISR_REACK Receive enable acknowledge flag : USART1_ISR_TEACK %1 21 lshift USART1_ISR bis! ; \ USART1_ISR_TEACK Transmit enable acknowledge flag : USART1_ISR_WUF %1 20 lshift USART1_ISR bis! ; \ USART1_ISR_WUF Wakeup from Stop mode flag : USART1_ISR_RWU %1 19 lshift USART1_ISR bis! ; \ USART1_ISR_RWU Receiver wakeup from Mute mode : USART1_ISR_SBKF %1 18 lshift USART1_ISR bis! ; \ USART1_ISR_SBKF Send break flag : USART1_ISR_CMF %1 17 lshift USART1_ISR bis! ; \ USART1_ISR_CMF character match flag : USART1_ISR_BUSY %1 16 lshift USART1_ISR bis! ; \ USART1_ISR_BUSY Busy flag : USART1_ISR_ABRF %1 15 lshift USART1_ISR bis! ; \ USART1_ISR_ABRF Auto baud rate flag : USART1_ISR_ABRE %1 14 lshift USART1_ISR bis! ; \ USART1_ISR_ABRE Auto baud rate error : USART1_ISR_EOBF %1 12 lshift USART1_ISR bis! ; \ USART1_ISR_EOBF End of block flag : USART1_ISR_RTOF %1 11 lshift USART1_ISR bis! ; \ USART1_ISR_RTOF Receiver timeout : USART1_ISR_CTS %1 10 lshift USART1_ISR bis! ; \ USART1_ISR_CTS CTS flag : USART1_ISR_CTSIF %1 9 lshift USART1_ISR bis! ; \ USART1_ISR_CTSIF CTS interrupt flag : USART1_ISR_LBDF %1 8 lshift USART1_ISR bis! ; \ USART1_ISR_LBDF LIN break detection flag : USART1_ISR_TXE %1 7 lshift USART1_ISR bis! ; \ USART1_ISR_TXE Transmit data register empty : USART1_ISR_TC %1 6 lshift USART1_ISR bis! ; \ USART1_ISR_TC Transmission complete : USART1_ISR_RXNE %1 5 lshift USART1_ISR bis! ; \ USART1_ISR_RXNE Read data register not empty : USART1_ISR_IDLE %1 4 lshift USART1_ISR bis! ; \ USART1_ISR_IDLE Idle line detected : USART1_ISR_ORE %1 3 lshift USART1_ISR bis! ; \ USART1_ISR_ORE Overrun error : USART1_ISR_NF %1 2 lshift USART1_ISR bis! ; \ USART1_ISR_NF Noise detected flag : USART1_ISR_FE %1 1 lshift USART1_ISR bis! ; \ USART1_ISR_FE Framing error : USART1_ISR_PE %1 0 lshift USART1_ISR bis! ; \ USART1_ISR_PE Parity error \ USART1_ICR (read-write) : USART1_ICR_WUCF %1 20 lshift USART1_ICR bis! ; \ USART1_ICR_WUCF Wakeup from Stop mode clear flag : USART1_ICR_CMCF %1 17 lshift USART1_ICR bis! ; \ USART1_ICR_CMCF Character match clear flag : USART1_ICR_EOBCF %1 12 lshift USART1_ICR bis! ; \ USART1_ICR_EOBCF End of timeout clear flag : USART1_ICR_RTOCF %1 11 lshift USART1_ICR bis! ; \ USART1_ICR_RTOCF Receiver timeout clear flag : USART1_ICR_CTSCF %1 9 lshift USART1_ICR bis! ; \ USART1_ICR_CTSCF CTS clear flag : USART1_ICR_LBDCF %1 8 lshift USART1_ICR bis! ; \ USART1_ICR_LBDCF LIN break detection clear flag : USART1_ICR_TCCF %1 6 lshift USART1_ICR bis! ; \ USART1_ICR_TCCF Transmission complete clear flag : USART1_ICR_IDLECF %1 4 lshift USART1_ICR bis! ; \ USART1_ICR_IDLECF Idle line detected clear flag : USART1_ICR_ORECF %1 3 lshift USART1_ICR bis! ; \ USART1_ICR_ORECF Overrun error clear flag : USART1_ICR_NCF %1 2 lshift USART1_ICR bis! ; \ USART1_ICR_NCF Noise detected clear flag : USART1_ICR_FECF %1 1 lshift USART1_ICR bis! ; \ USART1_ICR_FECF Framing error clear flag : USART1_ICR_PECF %1 0 lshift USART1_ICR bis! ; \ USART1_ICR_PECF Parity error clear flag \ USART1_RDR (read-only) : USART1_RDR_RDR ( %XXXXXXXXX -- ) 0 lshift USART1_RDR bis! ; \ USART1_RDR_RDR Receive data value \ USART1_TDR (read-write) : USART1_TDR_TDR ( %XXXXXXXXX -- ) 0 lshift USART1_TDR bis! ; \ USART1_TDR_TDR Transmit data value \ Flash_ACR () : Flash_ACR_LATENCY ( %XXX -- ) 0 lshift Flash_ACR bis! ; \ Flash_ACR_LATENCY LATENCY : Flash_ACR_PRFTBE %1 4 lshift Flash_ACR bis! ; \ Flash_ACR_PRFTBE PRFTBE : Flash_ACR_PRFTBS %1 5 lshift Flash_ACR bis! ; \ Flash_ACR_PRFTBS PRFTBS \ Flash_KEYR (write-only) : Flash_KEYR_FKEYR ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift Flash_KEYR bis! ; \ Flash_KEYR_FKEYR Flash Key \ Flash_OPTKEYR (write-only) : Flash_OPTKEYR_OPTKEYR ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift Flash_OPTKEYR bis! ; \ Flash_OPTKEYR_OPTKEYR Option byte key \ Flash_SR () : Flash_SR_EOP %1 5 lshift Flash_SR bis! ; \ Flash_SR_EOP End of operation : Flash_SR_WRPRT %1 4 lshift Flash_SR bis! ; \ Flash_SR_WRPRT Write protection error : Flash_SR_PGERR %1 2 lshift Flash_SR bis! ; \ Flash_SR_PGERR Programming error : Flash_SR_BSY %1 0 lshift Flash_SR bis! ; \ Flash_SR_BSY Busy \ Flash_CR (read-write) : Flash_CR_FORCE_OPTLOAD %1 13 lshift Flash_CR bis! ; \ Flash_CR_FORCE_OPTLOAD Force option byte loading : Flash_CR_EOPIE %1 12 lshift Flash_CR bis! ; \ Flash_CR_EOPIE End of operation interrupt enable : Flash_CR_ERRIE %1 10 lshift Flash_CR bis! ; \ Flash_CR_ERRIE Error interrupt enable : Flash_CR_OPTWRE %1 9 lshift Flash_CR bis! ; \ Flash_CR_OPTWRE Option bytes write enable : Flash_CR_LOCK %1 7 lshift Flash_CR bis! ; \ Flash_CR_LOCK Lock : Flash_CR_STRT %1 6 lshift Flash_CR bis! ; \ Flash_CR_STRT Start : Flash_CR_OPTER %1 5 lshift Flash_CR bis! ; \ Flash_CR_OPTER Option byte erase : Flash_CR_OPTPG %1 4 lshift Flash_CR bis! ; \ Flash_CR_OPTPG Option byte programming : Flash_CR_MER %1 2 lshift Flash_CR bis! ; \ Flash_CR_MER Mass erase : Flash_CR_PER %1 1 lshift Flash_CR bis! ; \ Flash_CR_PER Page erase : Flash_CR_PG %1 0 lshift Flash_CR bis! ; \ Flash_CR_PG Programming \ Flash_AR (write-only) : Flash_AR_FAR ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift Flash_AR bis! ; \ Flash_AR_FAR Flash address \ Flash_OBR (read-only) : Flash_OBR_Data1 ( %XXXXXXXX -- ) 24 lshift Flash_OBR bis! ; \ Flash_OBR_Data1 Data1 : Flash_OBR_Data0 ( %XXXXXXXX -- ) 16 lshift Flash_OBR bis! ; \ Flash_OBR_Data0 Data0 : Flash_OBR_VDDA_MONITOR %1 13 lshift Flash_OBR bis! ; \ Flash_OBR_VDDA_MONITOR VDDA_MONITOR : Flash_OBR_BOOT1 %1 12 lshift Flash_OBR bis! ; \ Flash_OBR_BOOT1 BOOT1 : Flash_OBR_nRST_STDBY %1 10 lshift Flash_OBR bis! ; \ Flash_OBR_nRST_STDBY nRST_STDBY : Flash_OBR_nRST_STOP %1 9 lshift Flash_OBR bis! ; \ Flash_OBR_nRST_STOP nRST_STOP : Flash_OBR_WDG_SW %1 8 lshift Flash_OBR bis! ; \ Flash_OBR_WDG_SW WDG_SW : Flash_OBR_LEVEL2_PROT %1 2 lshift Flash_OBR bis! ; \ Flash_OBR_LEVEL2_PROT Level 2 protection status : Flash_OBR_LEVEL1_PROT %1 1 lshift Flash_OBR bis! ; \ Flash_OBR_LEVEL1_PROT Level 1 protection status : Flash_OBR_OPTERR %1 0 lshift Flash_OBR bis! ; \ Flash_OBR_OPTERR Option byte error \ Flash_WRPR (read-only) : Flash_WRPR_WRP ( %XXXXXXXXXXXXXXXX -- ) 0 lshift Flash_WRPR bis! ; \ Flash_WRPR_WRP Write protect