\ TEMPLATE FILE for STM32F0xx
\ created by svdcutter for Mecrisp-Stellaris Forth by Matthias Koch
\ sdvcutter  takes a CMSIS-SVD file plus a hand edited config.xml file as input 
\ By Terry Porter "terry@tjporter.com.au", released under the GPL V2 Licence

 compiletoflash

\ available forth template words as selected by config.xml

$48000800 constant GPIOC ( General-purpose I/Os ) 
GPIOC $0 + constant GPIOC_MODER ( GPIO port mode register ) 
GPIOC $4 + constant GPIOC_OTYPER ( GPIO port output type register ) 
GPIOC $8 + constant GPIOC_OSPEEDR ( GPIO port output speed  register ) 
GPIOC $C + constant GPIOC_PUPDR ( GPIO port pull-up/pull-down  register ) 
GPIOC $10 + constant GPIOC_IDR ( GPIO port input data register ) 
GPIOC $14 + constant GPIOC_ODR ( GPIO port output data register ) 
GPIOC $18 + constant GPIOC_BSRR ( GPIO port bit set/reset  register ) 
GPIOC $1C + constant GPIOC_LCKR ( GPIO port configuration lock  register ) 
GPIOC $20 + constant GPIOC_AFRL ( GPIO alternate function low  register ) 
GPIOC $24 + constant GPIOC_AFRH ( GPIO alternate function high  register ) 
GPIOC $28 + constant GPIOC_BRR ( Port bit reset register ) 
: GPIOC_MODER. ." GPIOC_MODER (read-write) $" GPIOC_MODER @ hex. GPIOC_MODER 2b.  ;
: GPIOC_OTYPER. ." GPIOC_OTYPER (read-write) $" GPIOC_OTYPER @ hex. GPIOC_OTYPER 15b. ;
: GPIOC_OSPEEDR. ." GPIOC_OSPEEDR (read-write) $" GPIOC_OSPEEDR @ hex. GPIOC_OSPEEDR 2b.  ;
: GPIOC_PUPDR. ." GPIOC_PUPDR (read-write) $" GPIOC_PUPDR @ hex. GPIOC_PUPDR 2b.  ;
: GPIOC_IDR. ." GPIOC_IDR (read-only) $" GPIOC_IDR @ hex. GPIOC_IDR 15b. ;
: GPIOC_ODR. ." GPIOC_ODR (read-write) $" GPIOC_ODR @ hex. GPIOC_ODR 15b. ;
: GPIOC_BSRR. ." GPIOC_BSRR (write-only) $" GPIOC_BSRR @ hex. GPIOC_BSRR 1b.  ;
: GPIOC_LCKR. ." GPIOC_LCKR (read-write) $" GPIOC_LCKR @ hex. GPIOC_LCKR 1b.  ;
: GPIOC_AFRL. ." GPIOC_AFRL (read-write) $" GPIOC_AFRL @ hex. GPIOC_AFRL 4bl. ;
: GPIOC_AFRH. ." GPIOC_AFRH (read-write) $" GPIOC_AFRH @ hex. GPIOC_AFRH 4bh. ;
: GPIOC_BRR. ." GPIOC_BRR (write-only) $" GPIOC_BRR @ hex. GPIOC_BRR 15b. ;
: GPIOC.
GPIOC_MODER.
GPIOC_OTYPER.
GPIOC_OSPEEDR.
GPIOC_PUPDR.
GPIOC_IDR.
GPIOC_ODR.
GPIOC_BSRR.
GPIOC_LCKR.
GPIOC_AFRL.
GPIOC_AFRH.
GPIOC_BRR.
;

$48000400 constant GPIOB ( General-purpose I/Os ) 
GPIOB $0 + constant GPIOB_MODER ( GPIO port mode register ) 
GPIOB $4 + constant GPIOB_OTYPER ( GPIO port output type register ) 
GPIOB $8 + constant GPIOB_OSPEEDR ( GPIO port output speed  register ) 
GPIOB $C + constant GPIOB_PUPDR ( GPIO port pull-up/pull-down  register ) 
GPIOB $10 + constant GPIOB_IDR ( GPIO port input data register ) 
GPIOB $14 + constant GPIOB_ODR ( GPIO port output data register ) 
GPIOB $18 + constant GPIOB_BSRR ( GPIO port bit set/reset  register ) 
GPIOB $1C + constant GPIOB_LCKR ( GPIO port configuration lock  register ) 
GPIOB $20 + constant GPIOB_AFRL ( GPIO alternate function low  register ) 
GPIOB $24 + constant GPIOB_AFRH ( GPIO alternate function high  register ) 
GPIOB $28 + constant GPIOB_BRR ( Port bit reset register ) 
: GPIOB_MODER. ." GPIOB_MODER (read-write) $" GPIOB_MODER @ hex. GPIOB_MODER 2b.  ;
: GPIOB_OTYPER. ." GPIOB_OTYPER (read-write) $" GPIOB_OTYPER @ hex. GPIOB_OTYPER 15b. ;
: GPIOB_OSPEEDR. ." GPIOB_OSPEEDR (read-write) $" GPIOB_OSPEEDR @ hex. GPIOB_OSPEEDR 2b.  ;
: GPIOB_PUPDR. ." GPIOB_PUPDR (read-write) $" GPIOB_PUPDR @ hex. GPIOB_PUPDR 2b.  ;
: GPIOB_IDR. ." GPIOB_IDR (read-only) $" GPIOB_IDR @ hex. GPIOB_IDR 15b. ;
: GPIOB_ODR. ." GPIOB_ODR (read-write) $" GPIOB_ODR @ hex. GPIOB_ODR 15b. ;
: GPIOB_BSRR. ." GPIOB_BSRR (write-only) $" GPIOB_BSRR @ hex. GPIOB_BSRR 1b.  ;
: GPIOB_LCKR. ." GPIOB_LCKR (read-write) $" GPIOB_LCKR @ hex. GPIOB_LCKR 1b.  ;
: GPIOB_AFRL. ." GPIOB_AFRL (read-write) $" GPIOB_AFRL @ hex. GPIOB_AFRL 4bl. ;
: GPIOB_AFRH. ." GPIOB_AFRH (read-write) $" GPIOB_AFRH @ hex. GPIOB_AFRH 4bh. ;
: GPIOB_BRR. ." GPIOB_BRR (write-only) $" GPIOB_BRR @ hex. GPIOB_BRR 15b. ;
: GPIOB.
GPIOB_MODER.
GPIOB_OTYPER.
GPIOB_OSPEEDR.
GPIOB_PUPDR.
GPIOB_IDR.
GPIOB_ODR.
GPIOB_BSRR.
GPIOB_LCKR.
GPIOB_AFRL.
GPIOB_AFRH.
GPIOB_BRR.
;

$48000000 constant GPIOA ( General-purpose I/Os ) 
GPIOA $0 + constant GPIOA_MODER ( GPIO port mode register ) 
GPIOA $4 + constant GPIOA_OTYPER ( GPIO port output type register ) 
GPIOA $8 + constant GPIOA_OSPEEDR ( GPIO port output speed  register ) 
GPIOA $C + constant GPIOA_PUPDR ( GPIO port pull-up/pull-down  register ) 
GPIOA $10 + constant GPIOA_IDR ( GPIO port input data register ) 
GPIOA $14 + constant GPIOA_ODR ( GPIO port output data register ) 
GPIOA $18 + constant GPIOA_BSRR ( GPIO port bit set/reset  register ) 
GPIOA $1C + constant GPIOA_LCKR ( GPIO port configuration lock  register ) 
GPIOA $20 + constant GPIOA_AFRL ( GPIO alternate function low  register ) 
GPIOA $24 + constant GPIOA_AFRH ( GPIO alternate function high  register ) 
GPIOA $28 + constant GPIOA_BRR ( Port bit reset register ) 
: GPIOA_MODER. ." GPIOA_MODER (read-write) $" GPIOA_MODER @ hex. GPIOA_MODER 2b.  ;
: GPIOA_OTYPER. ." GPIOA_OTYPER (read-write) $" GPIOA_OTYPER @ hex. GPIOA_OTYPER 15b. ;
: GPIOA_OSPEEDR. ." GPIOA_OSPEEDR (read-write) $" GPIOA_OSPEEDR @ hex. GPIOA_OSPEEDR 2b.  ;
: GPIOA_PUPDR. ." GPIOA_PUPDR (read-write) $" GPIOA_PUPDR @ hex. GPIOA_PUPDR 2b.  ;
: GPIOA_IDR. ." GPIOA_IDR (read-only) $" GPIOA_IDR @ hex. GPIOA_IDR 15b. ;
: GPIOA_ODR. ." GPIOA_ODR (read-write) $" GPIOA_ODR @ hex. GPIOA_ODR 15b. ;
: GPIOA_BSRR. ." GPIOA_BSRR (write-only) $" GPIOA_BSRR @ hex. GPIOA_BSRR 1b.  ;
: GPIOA_LCKR. ." GPIOA_LCKR (read-write) $" GPIOA_LCKR @ hex. GPIOA_LCKR 1b.  ;
: GPIOA_AFRL. ." GPIOA_AFRL (read-write) $" GPIOA_AFRL @ hex. GPIOA_AFRL 4bl. ;
: GPIOA_AFRH. ." GPIOA_AFRH (read-write) $" GPIOA_AFRH @ hex. GPIOA_AFRH 4bh. ;
: GPIOA_BRR. ." GPIOA_BRR (write-only) $" GPIOA_BRR @ hex. GPIOA_BRR 15b. ;
: GPIOA.
GPIOA_MODER.
GPIOA_OTYPER.
GPIOA_OSPEEDR.
GPIOA_PUPDR.
GPIOA_IDR.
GPIOA_ODR.
GPIOA_BSRR.
GPIOA_LCKR.
GPIOA_AFRL.
GPIOA_AFRH.
GPIOA_BRR.
;

$40001000 constant TIM6 ( Basic-timers ) 
TIM6 $0 + constant TIM6_CR1 ( control register 1 ) 
TIM6 $4 + constant TIM6_CR2 ( control register 2 ) 
TIM6 $C + constant TIM6_DIER ( DMA/Interrupt enable register ) 
TIM6 $10 + constant TIM6_SR ( status register ) 
TIM6 $14 + constant TIM6_EGR ( event generation register ) 
TIM6 $24 + constant TIM6_CNT ( counter ) 
TIM6 $28 + constant TIM6_PSC ( prescaler ) 
TIM6 $2C + constant TIM6_ARR ( auto-reload register ) 
: TIM6_CR1. ." TIM6_CR1 (read-write) $" TIM6_CR1 @ hex. TIM6_CR1 1b. ;
: TIM6_CR2. ." TIM6_CR2 (read-write) $" TIM6_CR2 @ hex. TIM6_CR2 1b. ;
: TIM6_DIER. ." TIM6_DIER (read-write) $" TIM6_DIER @ hex. TIM6_DIER 1b. ;
: TIM6_SR. ." TIM6_SR (read-write) $" TIM6_SR @ hex. TIM6_SR 1b. ;
: TIM6_EGR. ." TIM6_EGR (write-only) $" TIM6_EGR @ hex. TIM6_EGR 1b. ;
: TIM6_CNT. ." TIM6_CNT (read-write) $" TIM6_CNT @ hex. TIM6_CNT 1b. ;
: TIM6_PSC. ." TIM6_PSC (read-write) $" TIM6_PSC @ hex. TIM6_PSC 1b. ;
: TIM6_ARR. ." TIM6_ARR (read-write) $" TIM6_ARR @ hex. TIM6_ARR 1b. ;
: TIM6.
TIM6_CR1.
TIM6_CR2.
TIM6_DIER.
TIM6_SR.
TIM6_EGR.
TIM6_CNT.
TIM6_PSC.
TIM6_ARR.
;

$40010400 constant EXTI ( External interrupt/event  controller ) 
EXTI $0 + constant EXTI_IMR ( Interrupt mask register  EXTI_IMR ) 
EXTI $4 + constant EXTI_EMR ( Event mask register EXTI_EMR ) 
EXTI $8 + constant EXTI_RTSR ( Rising Trigger selection register  EXTI_RTSR ) 
EXTI $C + constant EXTI_FTSR ( Falling Trigger selection register  EXTI_FTSR ) 
EXTI $10 + constant EXTI_SWIER ( Software interrupt event register  EXTI_SWIER ) 
EXTI $14 + constant EXTI_PR ( Pending register EXTI_PR ) 
: EXTI_IMR. ." EXTI_IMR (read-write) $" EXTI_IMR @ hex. EXTI_IMR 1b. ;
: EXTI_EMR. ." EXTI_EMR (read-write) $" EXTI_EMR @ hex. EXTI_EMR 1b. ;
: EXTI_RTSR. ." EXTI_RTSR (read-write) $" EXTI_RTSR @ hex. EXTI_RTSR 1b. ;
: EXTI_FTSR. ." EXTI_FTSR (read-write) $" EXTI_FTSR @ hex. EXTI_FTSR 1b. ;
: EXTI_SWIER. ." EXTI_SWIER (read-write) $" EXTI_SWIER @ hex. EXTI_SWIER 1b. ;
: EXTI_PR. ." EXTI_PR (read-write) $" EXTI_PR @ hex. EXTI_PR 1b. ;
: EXTI.
EXTI_IMR.
EXTI_EMR.
EXTI_RTSR.
EXTI_FTSR.
EXTI_SWIER.
EXTI_PR.
;

$E000E100 constant NVIC ( Nested Vectored Interrupt  Controller ) 
NVIC $0 + constant NVIC_ISER ( Interrupt Set Enable Register ) 
NVIC $80 + constant NVIC_ICER ( Interrupt Clear Enable  Register ) 
NVIC $100 + constant NVIC_ISPR ( Interrupt Set-Pending Register ) 
NVIC $180 + constant NVIC_ICPR ( Interrupt Clear-Pending  Register ) 
NVIC $300 + constant NVIC_IPR0 ( Interrupt Priority Register 0 ) 
NVIC $304 + constant NVIC_IPR1 ( Interrupt Priority Register 1 ) 
NVIC $308 + constant NVIC_IPR2 ( Interrupt Priority Register 2 ) 
NVIC $30C + constant NVIC_IPR3 ( Interrupt Priority Register 3 ) 
NVIC $310 + constant NVIC_IPR4 ( Interrupt Priority Register 4 ) 
NVIC $314 + constant NVIC_IPR5 ( Interrupt Priority Register 5 ) 
NVIC $318 + constant NVIC_IPR6 ( Interrupt Priority Register 6 ) 
NVIC $31C + constant NVIC_IPR7 ( Interrupt Priority Register 7 ) 
: NVIC_ISER. ." NVIC_ISER (read-write) $" NVIC_ISER @ hex. NVIC_ISER 1b. ;
: NVIC_ICER. ." NVIC_ICER (read-write) $" NVIC_ICER @ hex. NVIC_ICER 1b. ;
: NVIC_ISPR. ." NVIC_ISPR (read-write) $" NVIC_ISPR @ hex. NVIC_ISPR 1b. ;
: NVIC_ICPR. ." NVIC_ICPR (read-write) $" NVIC_ICPR @ hex. NVIC_ICPR 1b. ;
: NVIC_IPR0. ." NVIC_IPR0 (read-write) $" NVIC_IPR0 @ hex. NVIC_IPR0 1b. ;
: NVIC_IPR1. ." NVIC_IPR1 (read-write) $" NVIC_IPR1 @ hex. NVIC_IPR1 1b. ;
: NVIC_IPR2. ." NVIC_IPR2 (read-write) $" NVIC_IPR2 @ hex. NVIC_IPR2 1b. ;
: NVIC_IPR3. ." NVIC_IPR3 (read-write) $" NVIC_IPR3 @ hex. NVIC_IPR3 1b. ;
: NVIC_IPR4. ." NVIC_IPR4 (read-write) $" NVIC_IPR4 @ hex. NVIC_IPR4 1b. ;
: NVIC_IPR5. ." NVIC_IPR5 (read-write) $" NVIC_IPR5 @ hex. NVIC_IPR5 1b. ;
: NVIC_IPR6. ." NVIC_IPR6 (read-write) $" NVIC_IPR6 @ hex. NVIC_IPR6 1b. ;
: NVIC_IPR7. ." NVIC_IPR7 (read-write) $" NVIC_IPR7 @ hex. NVIC_IPR7 1b. ;
: NVIC.
NVIC_ISER.
NVIC_ICER.
NVIC_ISPR.
NVIC_ICPR.
NVIC_IPR0.
NVIC_IPR1.
NVIC_IPR2.
NVIC_IPR3.
NVIC_IPR4.
NVIC_IPR5.
NVIC_IPR6.
NVIC_IPR7.
;

$40021000 constant RCC ( Reset and clock control ) 
RCC $0 + constant RCC_CR ( Clock control register ) 
RCC $4 + constant RCC_CFGR ( Clock configuration register  RCC_CFGR ) 
RCC $8 + constant RCC_CIR ( Clock interrupt register  RCC_CIR ) 
RCC $C + constant RCC_APB2RSTR ( APB2 peripheral reset register  RCC_APB2RSTR ) 
RCC $10 + constant RCC_APB1RSTR ( APB1 peripheral reset register  RCC_APB1RSTR ) 
RCC $14 + constant RCC_AHBENR ( AHB Peripheral Clock enable register  RCC_AHBENR ) 
RCC $18 + constant RCC_APB2ENR ( APB2 peripheral clock enable register  RCC_APB2ENR ) 
RCC $1C + constant RCC_APB1ENR ( APB1 peripheral clock enable register  RCC_APB1ENR ) 
RCC $20 + constant RCC_BDCR ( Backup domain control register  RCC_BDCR ) 
RCC $24 + constant RCC_CSR ( Control/status register  RCC_CSR ) 
RCC $28 + constant RCC_AHBRSTR ( AHB peripheral reset register ) 
RCC $2C + constant RCC_CFGR2 ( Clock configuration register 2 ) 
RCC $30 + constant RCC_CFGR3 ( Clock configuration register 3 ) 
RCC $34 + constant RCC_CR2 ( Clock control register 2 ) 
: RCC_CR. ." RCC_CR () $" RCC_CR @ hex. RCC_CR RCC_CR.. ;
: RCC_CFGR. ." RCC_CFGR () $" RCC_CFGR @ hex. RCC_CFGR RCC_CFGR.. ;
: RCC_CIR. ." RCC_CIR () $" RCC_CIR @ hex. RCC_CIR 1b. ;
: RCC_APB2RSTR. ." RCC_APB2RSTR (read-write) $" RCC_APB2RSTR @ hex. RCC_APB2RSTR 1b. ;
: RCC_APB1RSTR. ." RCC_APB1RSTR (read-write) $" RCC_APB1RSTR @ hex. RCC_APB1RSTR 1b. ;
: RCC_AHBENR. ." RCC_AHBENR (read-write) $" RCC_AHBENR @ hex. RCC_AHBENR RCC_AHBENR.. ;
: RCC_APB2ENR. ." RCC_APB2ENR (read-write) $" RCC_APB2ENR @ hex. RCC_APB2ENR RCC_APB2ENR.. ;
: RCC_APB1ENR. ." RCC_APB1ENR (read-write) $" RCC_APB1ENR @ hex. RCC_APB1ENR RCC_APB1ENR.. ;
: RCC_BDCR. ." RCC_BDCR () $" RCC_BDCR @ hex. RCC_BDCR 1b. ;
: RCC_CSR. ." RCC_CSR () $" RCC_CSR @ hex. RCC_CSR RCC_CSR.. ;
: RCC_AHBRSTR. ." RCC_AHBRSTR (read-write) $" RCC_AHBRSTR @ hex. RCC_AHBRSTR 15b. ;
: RCC_CFGR2. ." RCC_CFGR2 (read-write) $" RCC_CFGR2 @ hex. RCC_CFGR2 RCC_CFGR2.. ;
: RCC_CFGR3. ." RCC_CFGR3 (read-write) $" RCC_CFGR3 @ hex. RCC_CFGR3 RCC_CFGR3.. ;
: RCC_CR2. ." RCC_CR2 () $" RCC_CR2 @ hex. RCC_CR2 RCC_CR2.. ;
: RCC.
RCC_CR.
RCC_CFGR.
RCC_CIR.
RCC_APB2RSTR.
RCC_APB1RSTR.
RCC_AHBENR.
RCC_APB2ENR.
RCC_APB1ENR.
RCC_BDCR.
RCC_CSR.
RCC_AHBRSTR.
RCC_CFGR2.
RCC_CFGR3.
RCC_CR2.
;

$40010000 constant SYSCFG ( System configuration controller ) 
SYSCFG $0 + constant SYSCFG_CFGR1 ( configuration register 1 ) 
SYSCFG $8 + constant SYSCFG_EXTICR1 ( external interrupt configuration register  1 ) 
SYSCFG $C + constant SYSCFG_EXTICR2 ( external interrupt configuration register  2 ) 
SYSCFG $10 + constant SYSCFG_EXTICR3 ( external interrupt configuration register  3 ) 
SYSCFG $14 + constant SYSCFG_EXTICR4 ( external interrupt configuration register  4 ) 
SYSCFG $18 + constant SYSCFG_CFGR2 ( configuration register 2 ) 
: SYSCFG_CFGR1. ." SYSCFG_CFGR1 (read-write) $" SYSCFG_CFGR1 @ hex. SYSCFG_CFGR1 1b. ;
: SYSCFG_EXTICR1. ." SYSCFG_EXTICR1 (read-write) $" SYSCFG_EXTICR1 @ hex. SYSCFG_EXTICR1 1b. ;
: SYSCFG_EXTICR2. ." SYSCFG_EXTICR2 (read-write) $" SYSCFG_EXTICR2 @ hex. SYSCFG_EXTICR2 1b. ;
: SYSCFG_EXTICR3. ." SYSCFG_EXTICR3 (read-write) $" SYSCFG_EXTICR3 @ hex. SYSCFG_EXTICR3 1b. ;
: SYSCFG_EXTICR4. ." SYSCFG_EXTICR4 (read-write) $" SYSCFG_EXTICR4 @ hex. SYSCFG_EXTICR4 1b. ;
: SYSCFG_CFGR2. ." SYSCFG_CFGR2 (read-write) $" SYSCFG_CFGR2 @ hex. SYSCFG_CFGR2 1b. ;
: SYSCFG.
SYSCFG_CFGR1.
SYSCFG_EXTICR1.
SYSCFG_EXTICR2.
SYSCFG_EXTICR3.
SYSCFG_EXTICR4.
SYSCFG_CFGR2.
;

$40013800 constant USART1 ( Universal synchronous asynchronous receiver  transmitter ) 
USART1 $0 + constant USART1_CR1 ( Control register 1 ) 
USART1 $4 + constant USART1_CR2 ( Control register 2 ) 
USART1 $8 + constant USART1_CR3 ( Control register 3 ) 
USART1 $C + constant USART1_BRR ( Baud rate register ) 
USART1 $10 + constant USART1_GTPR ( Guard time and prescaler  register ) 
USART1 $14 + constant USART1_RTOR ( Receiver timeout register ) 
USART1 $18 + constant USART1_RQR ( Request register ) 
USART1 $1C + constant USART1_ISR ( Interrupt & status  register ) 
USART1 $20 + constant USART1_ICR ( Interrupt flag clear register ) 
USART1 $24 + constant USART1_RDR ( Receive data register ) 
USART1 $28 + constant USART1_TDR ( Transmit data register ) 
: USART1_CR1. ." USART1_CR1 (read-write) $" USART1_CR1 @ hex. USART1_CR1 1b. ;
: USART1_CR2. ." USART1_CR2 (read-write) $" USART1_CR2 @ hex. USART1_CR2 1b. ;
: USART1_CR3. ." USART1_CR3 (read-write) $" USART1_CR3 @ hex. USART1_CR3 1b. ;
: USART1_BRR. ." USART1_BRR (read-write) $" USART1_BRR @ hex. USART1_BRR 1b. ;
: USART1_GTPR. ." USART1_GTPR (read-write) $" USART1_GTPR @ hex. USART1_GTPR 1b. ;
: USART1_RTOR. ." USART1_RTOR (read-write) $" USART1_RTOR @ hex. USART1_RTOR 1b. ;
: USART1_RQR. ." USART1_RQR (read-write) $" USART1_RQR @ hex. USART1_RQR 1b. ;
: USART1_ISR. ." USART1_ISR (read-only) $" USART1_ISR @ hex. USART1_ISR 1b. ;
: USART1_ICR. ." USART1_ICR (read-write) $" USART1_ICR @ hex. USART1_ICR 1b. ;
: USART1_RDR. ." USART1_RDR (read-only) $" USART1_RDR @ hex. USART1_RDR 1b. ;
: USART1_TDR. ." USART1_TDR (read-write) $" USART1_TDR @ hex. USART1_TDR 1b. ;
: USART1.
USART1_CR1.
USART1_CR2.
USART1_CR3.
USART1_BRR.
USART1_GTPR.
USART1_RTOR.
USART1_RQR.
USART1_ISR.
USART1_ICR.
USART1_RDR.
USART1_TDR.
;

$40022000 constant Flash ( Flash ) 
Flash $0 + constant Flash_ACR ( Flash access control register ) 
Flash $4 + constant Flash_KEYR ( Flash key register ) 
Flash $8 + constant Flash_OPTKEYR ( Flash option key register ) 
Flash $C + constant Flash_SR ( Flash status register ) 
Flash $10 + constant Flash_CR ( Flash control register ) 
Flash $14 + constant Flash_AR ( Flash address register ) 
Flash $1C + constant Flash_OBR ( Option byte register ) 
Flash $20 + constant Flash_WRPR ( Write protection register ) 
: Flash_ACR. ." Flash_ACR () $" Flash_ACR @ hex. Flash_ACR 1b. ;
: Flash_KEYR. ." Flash_KEYR (write-only) $" Flash_KEYR @ hex. Flash_KEYR 1b. ;
: Flash_OPTKEYR. ." Flash_OPTKEYR (write-only) $" Flash_OPTKEYR @ hex. Flash_OPTKEYR 1b. ;
: Flash_SR. ." Flash_SR () $" Flash_SR @ hex. Flash_SR 1b. ;
: Flash_CR. ." Flash_CR (read-write) $" Flash_CR @ hex. Flash_CR 1b. ;
: Flash_AR. ." Flash_AR (write-only) $" Flash_AR @ hex. Flash_AR 1b. ;
: Flash_OBR. ." Flash_OBR (read-only) $" Flash_OBR @ hex. Flash_OBR 1b. ;
: Flash_WRPR. ." Flash_WRPR (read-only) $" Flash_WRPR @ hex. Flash_WRPR 1b. ;
: Flash.
Flash_ACR.
Flash_KEYR.
Flash_OPTKEYR.
Flash_SR.
Flash_CR.
Flash_AR.
Flash_OBR.
Flash_WRPR.
;


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