\ TEMPLATE FILE for STM32F0xx
\ created by svdcutter for Mecrisp-Stellaris Forth by Matthias Koch
\ sdvcutter  takes a CMSIS-SVD file plus a hand edited config.xml file as input 
\ By Terry Porter "terry@tjporter.com.au"


compiletoflash

\ pretty printing words

 : b32loop. ( u -- ) \ print 1 bit groups
 0  <#
 31 0 DO 
 # 32 HOLD LOOP
 # #>
 TYPE ; 

: 1b. ( u -- ) cr 
." 3|3|2|2|2|2|2|2|2|2|2|2|1|1|1|1|1|1|1|1|1|1" cr
." 1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0 " cr
@ binary b32loop. decimal cr ;


: b8loop. ( u -- )
0 <#
7 0 DO
# # # #
32 HOLD
LOOP
# # # # 
#>
TYPE ;

: 4b. ( u -- ) cr \ Print 4 bit groups
."  07   06   05   04   03   02   01   00  " cr
@ binary b8loop. cr ;


: b16loop. ( u -- ) 0
<#
15 0 DO
# #
32 HOLD
LOOP
# #
#>
TYPE ;

: 2b. ( u -- ) cr \ Print 2 bit groups
." 15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00 " cr
@ binary b16loop. cr
;



\ available forth template words as selected by config.xml

$48000400 constant GPIOB
GPIOB $0 + constant GPIOB_MODER
GPIOB $4 + constant GPIOB_OTYPER
GPIOB $8 + constant GPIOB_OSPEEDR
GPIOB $C + constant GPIOB_PUPDR
GPIOB $10 + constant GPIOB_IDR
GPIOB $14 + constant GPIOB_ODR
GPIOB $18 + constant GPIOB_BSRR
GPIOB $1C + constant GPIOB_LCKR
GPIOB $20 + constant GPIOB_AFRL
GPIOB $24 + constant GPIOB_AFRH
GPIOB $28 + constant GPIOB_BRR
: GPIOB. cr
." GPIOB_MODER $" GPIOB_MODER @ hex. GPIOB_MODER 1b.
." GPIOB_OTYPER $" GPIOB_OTYPER @ hex. GPIOB_OTYPER 1b.
." GPIOB_OSPEEDR $" GPIOB_OSPEEDR @ hex. GPIOB_OSPEEDR 1b.
." GPIOB_PUPDR $" GPIOB_PUPDR @ hex. GPIOB_PUPDR 1b.
." GPIOB_IDR $" GPIOB_IDR @ hex. GPIOB_IDR 1b.
." GPIOB_ODR $" GPIOB_ODR @ hex. GPIOB_ODR 1b.
." GPIOB_BSRR $" GPIOB_BSRR @ hex. GPIOB_BSRR 1b.
." GPIOB_LCKR $" GPIOB_LCKR @ hex. GPIOB_LCKR 1b.
." GPIOB_AFRL $" GPIOB_AFRL @ hex. GPIOB_AFRL 1b.
." GPIOB_AFRH $" GPIOB_AFRH @ hex. GPIOB_AFRH 1b.
." GPIOB_BRR $" GPIOB_BRR @ hex. GPIOB_BRR 1b.
;

$40002000 constant TIM14
TIM14 $0 + constant TIM14_CR1
TIM14 $C + constant TIM14_DIER
TIM14 $10 + constant TIM14_SR
TIM14 $14 + constant TIM14_EGR
TIM14 $18 + constant TIM14_CCMR1_Output
TIM14 $18 + constant TIM14_CCMR1_Input
TIM14 $20 + constant TIM14_CCER
TIM14 $24 + constant TIM14_CNT
TIM14 $28 + constant TIM14_PSC
TIM14 $2C + constant TIM14_ARR
TIM14 $34 + constant TIM14_CCR1
TIM14 $50 + constant TIM14_OR
: TIM14. cr
." TIM14_CR1 $" TIM14_CR1 @ hex. TIM14_CR1 1b.
." TIM14_DIER $" TIM14_DIER @ hex. TIM14_DIER 1b.
." TIM14_SR $" TIM14_SR @ hex. TIM14_SR 1b.
." TIM14_EGR $" TIM14_EGR @ hex. TIM14_EGR 1b.
." TIM14_CCMR1_Output $" TIM14_CCMR1_Output @ hex. TIM14_CCMR1_Output 1b.
." TIM14_CCMR1_Input $" TIM14_CCMR1_Input @ hex. TIM14_CCMR1_Input 1b.
." TIM14_CCER $" TIM14_CCER @ hex. TIM14_CCER 1b.
." TIM14_CNT $" TIM14_CNT @ hex. TIM14_CNT 1b.
." TIM14_PSC $" TIM14_PSC @ hex. TIM14_PSC 1b.
." TIM14_ARR $" TIM14_ARR @ hex. TIM14_ARR 1b.
." TIM14_CCR1 $" TIM14_CCR1 @ hex. TIM14_CCR1 1b.
." TIM14_OR $" TIM14_OR @ hex. TIM14_OR 1b.
;

$40021000 constant RCC
RCC $0 + constant RCC_CR
RCC $4 + constant RCC_CFGR
RCC $8 + constant RCC_CIR
RCC $C + constant RCC_APB2RSTR
RCC $10 + constant RCC_APB1RSTR
RCC $14 + constant RCC_AHBENR
RCC $18 + constant RCC_APB2ENR
RCC $1C + constant RCC_APB1ENR
RCC $20 + constant RCC_BDCR
RCC $24 + constant RCC_CSR
RCC $28 + constant RCC_AHBRSTR
RCC $2C + constant RCC_CFGR2
RCC $30 + constant RCC_CFGR3
RCC $34 + constant RCC_CR2
: RCC. cr
." RCC_CR $" RCC_CR @ hex. RCC_CR 1b.
." RCC_CFGR $" RCC_CFGR @ hex. RCC_CFGR 1b.
." RCC_CIR $" RCC_CIR @ hex. RCC_CIR 1b.
." RCC_APB2RSTR $" RCC_APB2RSTR @ hex. RCC_APB2RSTR 1b.
." RCC_APB1RSTR $" RCC_APB1RSTR @ hex. RCC_APB1RSTR 1b.
." RCC_AHBENR $" RCC_AHBENR @ hex. RCC_AHBENR 1b.
." RCC_APB2ENR $" RCC_APB2ENR @ hex. RCC_APB2ENR 1b.
." RCC_APB1ENR $" RCC_APB1ENR @ hex. RCC_APB1ENR 1b.
." RCC_BDCR $" RCC_BDCR @ hex. RCC_BDCR 1b.
." RCC_CSR $" RCC_CSR @ hex. RCC_CSR 1b.
." RCC_AHBRSTR $" RCC_AHBRSTR @ hex. RCC_AHBRSTR 1b.
." RCC_CFGR2 $" RCC_CFGR2 @ hex. RCC_CFGR2 1b.
." RCC_CFGR3 $" RCC_CFGR3 @ hex. RCC_CFGR3 1b.
." RCC_CR2 $" RCC_CR2 @ hex. RCC_CR2 1b.
;

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