.. index:: svd2mem: supplement 1 .. _svd2mem-s1: Svd2mem Sqlite Supplement-1 =========================== Denoted by \*.sqlite.memmap-s1.db This supplement adds -------------------- * Relative addressing of BASE and OFFSET Example ^^^^^^^ MCU DB's Supplied ----------------- Texas Instruments MSP430 ^^^^^^^^^^^^^^^^^^^^^^^^ * MSP430F2013 * MSP430g2553 STM32F ^^^^^^ * STM32F051 * STM32F103xx * STM32F30x * STM32F407 * STM32F411xx * STM32F7x * STM32H7x3 * STM32L07x **Have you ever wondered how the STM32F and MSP430 timer compare ?** *SVD2MEM* provides a easy and fast way to compare peripherals based on register complexity compared to reading the relevant technical manuals. STM32F051 Peripherals --------------------- :: sqlite> .tables ADC DAC Flash GPIOD I2C2 RCC SYSCFG TIM16 TIM6 WWDG CEC DBGMCU GPIOA GPIOE IWDG RTC TIM1 TIM17 TSC COMP DMA GPIOB GPIOF NVIC SPI1 TIM14 TIM2 USART1 CRC EXTI GPIOC I2C1 PWR SPI2 TIM15 TIM3 USART2 The STM32F051 most complex Timer TIM1 ------------------------------------- :: sqlite> SELECT * FROM 'TIM1'; TIM1 - - Advanced-timers TIM1_CR1 $40012C00 read-write control register 1 TIM1_CR2 $40012C04 read-write control register 2 TIM1_SMCR $40012C08 read-write slave mode control register TIM1_DIER $40012C0C read-write DMA/Interrupt enable register TIM1_SR $40012C10 read-write status register TIM1_EGR $40012C14 write-only event generation register TIM1_CCMR1_Output $40012C18 read-write capture/compare mode register output mode TIM1_CCMR1_Input $40012C18 read-write capture/compare mode register 1 input mode TIM1_CCMR2_Output $40012C1C read-write capture/compare mode register output mode TIM1_CCMR2_Input $40012C1C read-write capture/compare mode register 2 input mode TIM1_CCER $40012C20 read-write capture/compare enable register TIM1_CNT $40012C24 read-write counter TIM1_PSC $40012C28 read-write prescaler TIM1_ARR $40012C2C read-write auto-reload register TIM1_RCR $40012C30 read-write repetition counter register TIM1_CCR1 $40012C34 read-write capture/compare register 1 TIM1_CCR2 $40012C38 read-write capture/compare register 2 TIM1_CCR3 $40012C3C read-write capture/compare register 3 TIM1_CCR4 $40012C40 read-write capture/compare register 4 TIM1_BDTR $40012C44 read-write break and dead-time register TIM1_DCR $40012C48 read-write DMA control register TIM1_DMAR $40012C4C read-write DMA address for full transfer MSP430F2013 Peripherals ----------------------- :: sqlite> .tables Calibration_Data SD16_A1 Timer_A2 _INTERRUPTS Flash Special_Function USI Port_1_2 System_Clock Watchdog_Timer MSP430F2013 Timer_A2 ^^^^^^^^^^^^^^^^^^^^ :: sqlite> SELECT * FROM 'Timer_A2'; Timer_A2 - - Timer A2 Timer_A2_TAIV $302 Timer A Interrupt Vector Word Timer_A2_TACTL $352 Timer A Control