Atomic read/modify accesses

Basically this is the requirement that when a I/O port registers is read or modified, the whole register state is updated before anything else can access it.

Some keywords regarding Atomic operations.

• Unaligned data

• interrupts

Note

NOT all Mecrisp-Stellaris Words are Atomic. For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers

STM32

Some newer STM32 MCU are able to handle I/O port register half-word or byte writes atomically, but older MCU’s such as the STM32F10x cannot and these are disallowed to prevent issues.

STM32F0xx

Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIOx_ODR registers. In this way, there is no risk of an IRQ occurring between the read and the modify access.

STM32F10x

As used in the Blue Pill board.

Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words, (half-word or byte accesses are NOT allowed). The purpose of the GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIO registers. This way, there is no risk that an IRQ occurs between the read and the modify access.

Yet another reason not to use the Blue Pill.