MSP340

Mecrisp is for MSP430xx chips and not for Cortex-M like Mecrisp-Stellaris, nevertheless they are both written by Matthias Koch and have many similarities as far as Forth is concerned, but the hardware is totally different. Both Mecrisp and Mecrisp Stellaris are hosted on the same site.

See: https://sourceforge.net/projects/mecrisp/files/ for downloads.

Writeup for Mecrisp on MSP430: https://mecrisp-across-folkdoc.sourceforge.io/mecrisp.html

Unofficial mecrisp-across Doc: https://mecrisp-across-folkdoc.sourceforge.io/index.html

Svd2Mecrisp

Svd2mecrisp was created to take advantage of SVD files produced by Vadzim Dambrouski’s https://github.com/pftbest/msp430_svd which uses DSLITE files released by Ti and processes them with the Rust programming language.

Some features:- * Produces a Memory Map file you can upload via the Mecrisp serial terminal * Creates a Register-Reference file where you can copy and paste Bitfields you need into your program. Search this file using names from the Ti PDF’s for rapid location and use. * Includes helpful longer descriptions for Registers and Bitfields for less PDF reliance.

Download Svd2mecrisp HERE. Instructions are included along with a sample msp430g2553.svd.

Sample Svd2Mecrisp output

Memory Map File

Partial, example only

...
\ ***** ADC10 ***** \
$48  constant  ADC10DTC0
$49  constant  ADC10DTC1
$4A  constant  ADC10AE0
$1B0  constant  ADC10CTL0
$1B2  constant  ADC10CTL1
$1B4  constant  ADC10MEM
$1BC  constant  ADC10SA
...

Register Reference File

Partial, example only

...
\ ADC10CTL0 ( ADC10 Control 0 )

\ %1  0 lshift constant ADC10SC     ( ADC10 Start Conversion   Bit 0 Width 1 )

\ %1  1 lshift constant ENC     ( ADC10 Enable Conversion   Bit 1 Width 1 )

\ %1  2 lshift constant ADC10IFG     ( ADC10 Interrupt Flag   Bit 2 Width 1 )

\ %1  3 lshift constant ADC10IE     ( ADC10 Interrupt Enalbe   Bit 3 Width 1 )

\ %1  4 lshift constant ADC10ON     ( ADC10 On/Enable   Bit 4 Width 1 )

\ %1  5 lshift constant REFON     ( ADC10 Reference on   Bit 5 Width 1 )

\ %1  6 lshift constant REF2_5V     ( ADC10 Ref 0:1.5V / 1:2.5V   Bit 6 Width 1 )

\ %1  7 lshift constant MSC     ( ADC10 Multiple SampleConversion   Bit 7 Width 1 )

\ %1  8 lshift constant REFBURST     ( ADC10 Reference Burst Mode   Bit 8 Width 1 )

\ %1  9 lshift constant REFOUT     ( ADC10 Enalbe output of Ref.   Bit 9 Width 1 )

\ %1  10 lshift constant ADC10SR     ( ADC10 Sampling Rate 0:200ksps / 1:50ksps   Bit 10 Width 1 )

\ %xx  11 lshift constant ADC10SHT     ( ADC10 Sample Hold Select Bit: 0   Bit 11 Width 2 )
    \ %0: ADC10SHT_0      ( 4 x ADC10CLKs )
    \ %1: ADC10SHT_1      ( 8 x ADC10CLKs )
    \ %11: ADC10SHT_2      ( 16 x ADC10CLKs )
    \ %111: ADC10SHT_3      ( 64 x ADC10CLKs )

\ %xxx  13 lshift constant SREF     ( ADC10 Reference Select Bit: 0   Bit 13 Width 3 )
    \ %0: SREF_0      ( VR+ = AVCC and VR- = AVSS )
    \ %1: SREF_1      ( VR+ = VREF+ and VR- = AVSS )
    \ %11: SREF_2      ( VR+ = VEREF+ and VR- = AVSS )
    \ %111: SREF_3      ( VR+ = VEREF+ and VR- = AVSS )
    \ %1111: SREF_4      ( VR+ = AVCC and VR- = VREF-/VEREF- )
    \ %11111: SREF_5      ( VR+ = VREF+ and VR- = VREF-/VEREF- )
    \ %111111: SREF_6      ( VR+ = VEREF+ and VR- = VREF-/VEREF- )
    \ %1111111: SREF_7      ( VR+ = VEREF+ and VR- = VREF-/VEREF- )
...